专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20050044408A1 Low pin count docking architecture for a trusted platform 审中-公开
标题翻译：可靠平台的低引脚数对接架构
公开(公告)号：US20050044408A1
公开(公告)日：2005-02-24
申请号：US10643678
申请日：2003-08-18
申请人： Sundeep Bajikar , David Poisner , Leslie Cline , Edwin Pole
发明人： Sundeep Bajikar , David Poisner , Leslie Cline , Edwin Pole
IPC分类号： G06F21/00 , H04L9/00
CPC分类号： G06F21/85
摘要： A docking architecture for a notebook computer is described. Specifically, a circuit coupled to a Low Pin Count (LPC) bus monitors the LPC bus for trusted data cycles. If a trusted data cycle is detected, the circuit prevents the trusted data cycle from being available to a non-trusted component.
摘要翻译：描述了笔记本电脑的对接架构。具体地，耦合到低引脚计数（LPC）总线的电路监视LPC总线以获得可信数据周期。如果检测到受信任的数据周期，则该电路可防止可信数据周期对不可信任的组件可用。

2. 发明申请

US20060095806A1 Method and apparatus for enabling a low power mode for a processor 有权
标题翻译：用于为处理器启用低功率模式的方法和装置
公开(公告)号：US20060095806A1
公开(公告)日：2006-05-04
申请号：US11300716
申请日：2005-12-13
申请人： Xia Dai , John Horigan , Millind Mittal , Leslie Cline
发明人： Xia Dai , John Horigan , Millind Mittal , Leslie Cline
IPC分类号： G06F1/26
CPC分类号： G06F1/3203 , G06F12/0891
摘要： In accordance with an embodiment of the present invention, a triggering event is initiated to place a processor in a low power state. The processor may or may not flush a cache upon entering the low power state depending on a power status signal. The power status signal may indicated the relative priority of power reduction associated with placing the processor in the low power state without first flushing the cache versus an increase in soft error rate in the cache associated with reducing the voltage in the low power state.
摘要翻译：根据本发明的实施例，启动触发事件以将处理器置于低功率状态。根据电源状态信号，处理器可能进入或不进入低功率状态时刷新高速缓存。功率状态信号可以指示与将低处理器置于低功率状态相关联的功率降低的相对优先级，而无需首先刷新高速缓存，而与高功率状态中的电压降低相关联的高速缓存中的软错误率的增加。

3. 发明申请

US20060294406A1 Reducing storage data transfer interference with processor power management 有权
标题翻译：减少存储数据传输干扰与处理器电源管理
公开(公告)号：US20060294406A1
公开(公告)日：2006-12-28
申请号：US11165157
申请日：2005-06-23
申请人： Leslie Cline
发明人： Leslie Cline
IPC分类号： G06F1/32
CPC分类号： G06F1/3215
摘要： Systems and methods of managing power consumption provide for placing a processor in a non-snoopable state while a storage interface associated with the processor is enabled for bus mastering. In one embodiment, the bus mastering results in traffic between the storage interface and a storage device, where the traffic is monitored and the processor is placed a snoopable state when traffic is moving, and in the non-snoopable idle state if the traffic ceases for a period of time.
摘要翻译：管理功耗的系统和方法提供了将处理器置于不可窥探状态，而与处理器相关联的存储接口能够用于总线主控。在一个实施例中，总线主控导致存储接口和存储设备之间的业务，其中监视业务，并且当业务正在移动时将处理器置于可窥探状态，并且处于不可窥探空闲状态，如果业务停止一段时间。

4. 发明申请

US20060132109A1 Audio noise mitigation for power state transitions 失效
标题翻译：功率状态转换的音频噪声抑制
公开(公告)号：US20060132109A1
公开(公告)日：2006-06-22
申请号：US11019791
申请日：2004-12-21
申请人： Jorge Rodriguez , Leslie Cline , Barnes Cooper
发明人： Jorge Rodriguez , Leslie Cline , Barnes Cooper
IPC分类号： G05F1/40
CPC分类号： G06F1/3203
摘要： An audio noise mitigation approach. For one aspect, a first voltage associated with a first power management state is provided. A signal responsive to an indication associated with at least a first type of periodic exit event is received and responsive to the signal, a transition to a second voltage associated with a second state is initiated, a rate of the transition to the second voltage being slower than a similar voltage transition initiated in response to a non-periodic exit event.
摘要翻译：音频噪声缓解方法。一方面，提供与第一电源管理状态相关联的第一电压。接收响应于与至少第一类型的周期性退出事件相关联的指示的信号并且响应于该信号，开始向与第二状态相关联的第二电压的转变，到第二电压的转变的速率较慢而不是响应于非周期性退出事件而发起的类似电压转换。

5. 发明申请

US20060020835A1 Method and apparatus for dynamic DLL powerdown and memory self-refresh 有权
标题翻译：用于动态DLL掉电和内存自刷新的方法和装置
公开(公告)号：US20060020835A1
公开(公告)日：2006-01-26
申请号：US10899530
申请日：2004-07-26
申请人： Eric Samson , Aditya Navale , Leslie Cline
发明人： Eric Samson , Aditya Navale , Leslie Cline
IPC分类号： G06F1/26
CPC分类号： G06F1/3225
摘要： Embodiments of the present invention provide a method and apparatus for conserving power in an electronic device. In particular, embodiments of the present invention dynamically place the memory in self-refresh and chipset clock circuits in power down mode while keeping the isochronous streams (such as display) updated and servicing bus master cycles in a power savings mode.
摘要翻译：本发明的实施例提供了一种用于在电子设备中节省功率的方法和装置。特别地，本发明的实施例将存储器动态地将自刷新和芯片组时钟电路放置在断电模式中，同时保持同步流（例如显示）被更新并且在节电模式下维持总线主控周期。

6. 发明申请

US20070005859A1 Method and apparatus to quiesce USB activities using interrupt descriptor caching and asynchronous notifications 有权
标题翻译：使用中断描述符缓存和异步通知来停止USB活动的方法和设备
公开(公告)号：US20070005859A1
公开(公告)日：2007-01-04
申请号：US11171833
申请日：2005-06-29
申请人： Paul Diefenbaugh , James Kardach , Barnes Cooper , Leslie Cline
发明人： Paul Diefenbaugh , James Kardach , Barnes Cooper , Leslie Cline
IPC分类号： G06F13/24
CPC分类号： G06F13/24 , G06F13/12
摘要： In one embodiment, a data processing system includes, but is not limited to, a processor, a memory coupled to the processor, and a universal serial bus (USB) controller coupled to the processor and the memory. The USB controller includes a local memory to cache at least one activity descriptor of at least a portion of a periodic schedule having multiple frames stored in the main memory. The USB controller defers to service an active USB device described by one of the activity descriptors until a corresponding frame is scheduled to be serviced subsequently. Other methods and apparatuses are also described.
摘要翻译：在一个实施例中，数据处理系统包括但不限于处理器，耦合到处理器的存储器以及耦合到处理器和存储器的通用串行总线（USB）控制器。 USB控制器包括本地存储器，以缓存具有存储在主存储器中的多个帧的周期性调度的至少一部分的至少一个活动描述符。 USB控制器延迟服务于其中一个活动描述符描述的活动USB设备，直到相应的帧被安排在随后的服务中。还描述了其它方法和装置。

7. 发明申请

US20060200690A1 System and method of coherent data transfer during processor idle states 有权
公开(公告)号：US20060200690A1
公开(公告)日：2006-09-07
申请号：US11074233
申请日：2005-03-05
申请人： Leslie Cline , Siripong Sritanyaratana , Alon Naveh , Shai Rotem , Eric Samson , Michael Derr
发明人： Leslie Cline , Siripong Sritanyaratana , Alon Naveh , Shai Rotem , Eric Samson , Michael Derr
IPC分类号： G06F1/32
CPC分类号： G06F12/0835 , G06F2212/1028 , Y02D10/13
摘要： Systems and methods of managing power provide for placing a processor in a non-snoopable state, where the processor is associated with a system memory. One or more data transfers between a controller and the system memory can be serviced while the processor is in the non-snoopable state. In one embodiment, it is determined that the processor has flushed an internal cache of the processor to the system memory before placing the processor in the non-snoopable state.

8. 发明申请

US20060123180A1 USB schedule prefetcher for low power 有权
标题翻译： USB调度预取器，用于低功耗
公开(公告)号：US20060123180A1
公开(公告)日：2006-06-08
申请号：US11004011
申请日：2004-12-02
申请人： Michael Derr , John Howard , Darren Abramson , Leslie Cline , Rob Strong
发明人： Michael Derr , John Howard , Darren Abramson , Leslie Cline , Rob Strong
IPC分类号： G06F13/36
CPC分类号： G06F13/28 , G06F2213/0042 , Y02D10/14
摘要： A circuit for monitoring future Universal Serial Bus (USB) activities is described. Specifically, the circuit may comprise a Direct Memory Access (DMA) engine schedule prefetcher. The DMA engine schedule prefetcher accesses linked list schedule structures in main memory. The structures are checked for future frames where the linked list has USB activity scheduled. A periodic DMA engine subsequently accesses main memory only during frames where USB traffic is scheduled.
摘要翻译：描述了用于监控未来通用串行总线（USB）活动的电路。具体地，电路可以包括直接存储器访问（DMA）引擎调度预取器。 DMA引擎调度预取器访问主内存中的链表列表调度结构。对结构进行检查，以便链接列表安排USB活动的未来帧。周期性DMA引擎随后仅在安排USB流量的帧期间访问主存储器。

9. 发明申请

US20050033869A1 Future activity list for peripheral bus host controller 有权
标题翻译：外设总线主机控制器的未来活动列表
公开(公告)号：US20050033869A1
公开(公告)日：2005-02-10
申请号：US10456185
申请日：2003-06-06
申请人： Leslie Cline
发明人： Leslie Cline
IPC分类号： G06F3/00 , G06F13/12
CPC分类号： G06F13/124 , Y02D10/14
摘要： One embodiment includes a future activity list (FAL) maintained within a peripheral bus host controller. The FAL includes information indicating for a number of peripheral bus frames whether those frames will have activity or are null. For frames that will have activity, the host controller performs a system memory read to gather information required to process the active frame. For frames that are null, the host controller does not perform the system memory read. A bus master status bit is pegged (continually set to “true”) by the host controller only when the host controller is processing an active frame. Because the bus master status bit is not pegged by the host controller during null frames, there is greater opportunity for an operating system to enter lower power states.
摘要翻译：一个实施例包括维护在外围总线主机控制器内的未来活动列表（FAL）。 FAL包括指示多个外围总线帧的信息，无论这些帧是否具有活动或为空。对于具有活动的帧，主机控制器执行系统内存读取，以收集处理活动帧所需的信息。对于为空的帧，主机控制器不执行系统内存读取。只有当主机控制器处理活动帧时，总线主控状态位被主机控制器固定（连续设置为“真”）。由于总线主控状态位在空帧期间不被主机控制器挂起，所以操作系统进入较低功率状态的机会更大。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式