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    • 1. 发明授权
    • High speed serial data transmission encoder
    • 高速串行数据传输编码器
    • US5912928A
    • 1999-06-15
    • US884117
    • 1997-06-27
    • Leonard R. ChiecoLouis T. FasanoKeith W. HeilmannMichael A. Sorna
    • Leonard R. ChiecoLouis T. FasanoKeith W. HeilmannMichael A. Sorna
    • H04L7/00H04L25/48H04L25/49H04L27/20H03M7/12H04L7/02
    • H04L7/0008H04L25/4904
    • A clock encoding circuit, e.g., for Manchester encoding, for high speed data transmission (IEEE 1394) and a circuit for controlling data and encoded clock transmission. The clock encoding circuit includes two parallel to serial shift registers, a DATA register and a STROBE register, receiving data in parallel and shifted out at 100 MHz, 200 MHz or 400 MHz. The STROBE register receives every other bit of the data inverted. When both registers are clocked at the data transmission rate, data is shifted out of DATA register and the transmission clock is encoded in STROBE, shifted out of the STROBE register. Bit inversion may be with invertors receiving data as it is passed to the DATA register, or alternatively, after it is loaded into the DATA register. The circuit for controlling DATA and STROBE transmission includes the clock encoding circuit, a frequency matching register array and a loopback shift register. A control word is loaded into the loopback register and loops through the loopback register at the transmission rate, triggering data transfers from the frequency matching register array to the DATA and STROBE registers. All or part of the DATA and STROBE register contents is transmitted depending on the transmission rate.
    • 时钟编码电路,例如用于曼彻斯特编码,用于高速数据传输(IEEE 1394)和用于控制数据和编码时钟传输的电路。 时钟编码电路包括两个并行到串行移位寄存器,一个DATA寄存器和一个STROBE寄存器,并行接收数据,并以100 MHz,200 MHz或400 MHz进行移出。 STROBE寄存器接收数据的每隔一位反转。 当两个寄存器以数据传输速率计时时,数据从DATA寄存器中移出,传输时钟以STROBE编码,移出STROBE寄存器。 位反转可以是反向器在数据被传递到DATA寄存器时接收数据,或者在其被加载到DATA寄存器之后。 用于控制DATA和STROBE传输的电路包括时钟编码电路,频率匹配寄存器阵列和环回移位寄存器。 控制字被加载到环回寄存器中,以传输速率循环回环寄存器,触发从频率匹配寄存器阵列到DATA和STROBE寄存器的数据传输。 根据传输速率传输全部或部分DATA和STROBE寄存器内容。
    • 2. 发明授权
    • Process independent source synchronous data capture apparatus and method
    • 过程独立源同步数据采集设备和方法
    • US06785832B2
    • 2004-08-31
    • US09887792
    • 2001-06-22
    • Leonard R. ChiecoLouis T. FasanoMichael A. Sorna
    • Leonard R. ChiecoLouis T. FasanoMichael A. Sorna
    • G06F112
    • H04L7/0008
    • An apparatus for capturing a data signal sent from a transmitting source to a receiving element, the data signal being accompanied by a first clock signal in a source synchronous system. In an exemplary embodiment, the apparatus comprises a delay element having an input coupled to the first clock signal and an output producing a delayed first clock signal. The delay element further includes a plurality of delay latches, having a second clock signal as a clock input thereto, the second clock signal having a frequency which is a multiple of the frequency of the first clock signal. The data signal is captured by the receiving element when the receiving element is triggered by an edge of the delayed first clock signal.
    • 一种用于捕获从发送源发送到接收元件的数据信号的装置,所述数据信号伴随着源同步系统中的第一时钟信号。 在示例性实施例中,该装置包括具有耦合到第一时钟信号的输入和产生延迟的第一时钟信号的输出的延迟元件。 延迟元件还包括多个延迟锁存器,其具有作为其输入的时钟的第二时钟信号,第二时钟信号的频率是第一时钟信号的频率的倍数。 当接收元件被延迟的第一时钟信号的边沿触发时,接收元件捕获数据信号。