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1. 发明授权

US5963801A Method of forming retrograde well structures and punch-through barriers using low energy implants 失效
标题翻译：使用低能量植入物形成逆行井结构和穿通障碍的方法
公开(公告)号：US5963801A
公开(公告)日：1999-10-05
申请号：US770109
申请日：1996-12-19
申请人： Sheldon Aronowitz , Laique Khan , James Kimball
发明人： Sheldon Aronowitz , Laique Khan , James Kimball
IPC分类号： H01L21/265 , H01L21/8238 , H01L27/092
CPC分类号： H01L21/26586 , H01L21/26513 , H01L21/823892
摘要： A retrograde well in a CMOS device is formed by using a low energy ion implanter. Dopant atoms are implanted into a bare surface of the device's substrate, in a direction that is orthogonal to the surface of the substrate (for a substrate having a orientation). The well implant can be performed at an energy below 220 keV. Chained implants for a punch-through barrier in the retrograde well can be performed after the well implant. When the substrate is annealed, the punch-through barrier is activated at the same time as the retrograde well.
摘要翻译：通过使用低能离子注入机形成CMOS器件中的逆行阱。将掺杂原子沿着与衬底的表面（具有<100>取向的衬底）正交的方向注入器件衬底的裸露表面。可以在低于220keV的能量下进行井注入。逆行井中的穿通屏障的链接植入物可以在植入物之后进行。当衬底退火时，穿通屏障在逆行井的同时被激活。

2. 发明授权

US06180470B2 FETs having lightly doped drain regions that are shaped with counter and noncounter dorant elements 失效
标题翻译：具有轻掺杂漏极区域的FET，其被形成有反向和不对称的多个元件
公开(公告)号：US06180470B2
公开(公告)日：2001-01-30
申请号：US08770046
申请日：1996-12-19
申请人： Sheldon Aronowitz , Laique Khan , James Kimball
发明人： Sheldon Aronowitz , Laique Khan , James Kimball
IPC分类号： H01L21336
CPC分类号： H01L29/6659 , H01L21/2652 , H01L21/26586 , H01L29/1045 , H01L29/1083 , H01L29/7833 , Y10S438/925
摘要： Lifetime of a short-channel NMOS device is increased by modifying distributions of electrically active LDD dopant at boundaries of the device's LDD regions. The LDD dopant distributions are modified by implanting counter-dopants at the boundaries of the LDD regions. Group III counter-dopants such as boron and group IV elements such as silicon alter activation properties of the LDD dopant. The dopant distributions are modified at the device's n-junctions to reduce the maximum electric field displacement at an interface defined by the device's gate and substrate. The dopant distributions can be further modified to shape the n-junctions such that hot carriers are injected away from the gate.
摘要翻译：通过修改器件的LDD区域边界处的电活性LDD掺杂剂的分布来增加短沟道NMOS器件的寿命。通过在LDD区域的边界处注入反掺杂剂来修改LDD掺杂剂分布。 III族反掺杂剂如硼和IV族元素如硅改变LDD掺杂剂的活化性质。掺杂剂分布在器件的n结处修改，以减少由器件的栅极和衬底限定的界面处的最大电场位移。可以进一步修改掺杂剂分布以使n结成形，使得热载流子从栅极注入。

3. 发明授权

US5877530A Formation of gradient doped profile region between channel region and heavily doped source/drain contact region of MOS device in integrated circuit structure using a re-entrant gate electrode and a higher dose drain implantation 失效
标题翻译：在集成电路结构中MOS器件的沟道区域和重掺杂源极/漏极接触区域之间的梯度掺杂分布区域的形成使用入口栅电极和较高剂量漏极注入
公开(公告)号：US5877530A
公开(公告)日：1999-03-02
申请号：US690592
申请日：1996-07-31
申请人： Sheldon Aronowitz , Laique Khan , Philippe Schoenborn
发明人： Sheldon Aronowitz , Laique Khan , Philippe Schoenborn
IPC分类号： H01L21/28 , H01L21/336 , H01L29/423 , H01L29/78
CPC分类号： H01L29/6659 , H01L21/28114 , H01L29/42376 , H01L29/7833
摘要： A novel integrated circuit structure, and process for making same, is disclosed wherein a tapered or gradient doped profile region is provided in a semiconductor substrate between the heavily doped drain region and the channel region in the substrate comprising an MOS device. In the process of the invention, a re-entrant or tapered gate electrode, resembling an inverted trapezoid, is used as a mask during a first doping step at a dosage level higher than normally used to form a conventional LDD region. This doping step forms a doped region having a dopant gradient which gradually increases in dosage level with distance from the channel region. Conventional oxide spacers may then be formed on the sidewalls of the gate electrode followed by conventional high level doping to form the heavily doped source and drain region in the unmasked portions of the substrate between the oxide spacers and the field oxide isolation. Since the doped region beneath the oxide spacers includes a gradient doped profile region, with the lightest level of dopant adjacent the channel region (since more of the tapered gate electrode acted as a mask for the initial implantation), the overall dosage level used in the first implantation step to form the gradient doped profile region may be higher than the dosage level conventionally used to form a conventional LDD region. The resistance of the path between the heavily doped drain contact region and the channel region, which includes the gradient doped profile region, is therefore lower than the resistance of a conventional LDD region.
摘要翻译：公开了一种新颖的集成电路结构及其制造方法，其中在包括MOS器件的衬底中的重掺杂漏极区域和沟道区域之间的半导体衬底中提供锥形或梯度掺杂型态区域。在本发明的方法中，在第一掺杂步骤期间，以比通常用于形成常规LDD区域的剂量水平，使用类似倒梯形的入口或锥形栅极电极作为掩模。该掺杂步骤形成具有掺杂剂梯度的掺杂区域，其随着与沟道区域的距离而逐渐增加剂量水平。然后可以在栅电极的侧壁上形成常规的氧化物间隔物，接着是常规的高电平掺杂，以在氧化物间隔物和场氧化物隔离之间的衬底的未屏蔽部分中形成重掺杂的源极和漏极区。由于氧化物间隔物下面的掺杂区域包括梯度掺杂的轮廓区域，其中掺杂剂的最弱级别与沟道区域相邻（因为更多的锥形栅极电极用作初始注入的掩模），所以在形成梯度掺杂轮廓区域的第一注入步骤可以高于常规用于形成常规LDD区域的剂量水平。因此，重掺杂漏极接触区域和沟道区域（包括梯度掺杂分布区域）之间的路径电阻比常规LDD区域的电阻低。

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