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1. 发明申请

WO2011070506A3 COMPUTER-IMPLEMENTED METHOD OF PROCESSING RESOURCE MANAGEMENT 审中-公开
标题翻译：计算机实施的资源管理方法
公开(公告)号：WO2011070506A3
公开(公告)日：2011-08-11
申请号：PCT/IB2010055626
申请日：2010-12-07
申请人： IBM , HUNTER HILLERY C , LUIJTEN RONALD P , STANLEY-MARBELL PHILLIP
发明人： HUNTER HILLERY C , LUIJTEN RONALD P , STANLEY-MARBELL PHILLIP
IPC分类号： G06F9/50 , G06F9/48 , G06F12/08 , G06F12/12
CPC分类号： G06F9/4856 , G06F9/5033 , G06F2212/271
摘要： A computer-implemented method for managing processing resources of a computerized system having at least a first processor and a second processor, each of the processors operatively interconnected to a memory storing a set of data to be processed by a processor, the method comprising: monitoring data accessed by the first processor while executing; and if the second processor is at a shorter distance than the first processor from the monitored data, instructing to interrupt execution at the first processor and resume the execution at the second processor.
摘要翻译：一种用于管理具有至少第一处理器和第二处理器的计算机化系统的处理资源的计算机实现的方法，所述处理器中的每一个可操作地互连到存储将由处理器处理的一组数据的存储器，所述方法包括：监视在执行时由第一处理器访问的数据; 以及如果所述第二处理器与所述第一处理器之间的距离比所述监控数据更短，则指示中断所述第一处理器处的执行并且继续所述第二处理器处的所述执行。

2. 发明申请

WO2002069668A1 SWITCHING ARRANGEMENT AND METHOD WITH SEPARATED OUTPUT BUFFERS 审中-公开
标题翻译：具有分离输出缓冲器的切换布局和方法
公开(公告)号：WO2002069668A1
公开(公告)日：2002-09-06
申请号：PCT/IB2002/000548
申请日：2002-02-25
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , BENNER, Alan, F. , ENGBERSEN, Antonius , GOLDRIAN, Gottfried, A. , LUIJTEN, Ronald, P.
发明人： BENNER, Alan, F. , ENGBERSEN, Antonius , GOLDRIAN, Gottfried, A. , LUIJTEN, Ronald, P.
IPC分类号： H04Q11/04
CPC分类号： H04L49/3081 , H04L49/203 , H04L2012/5635 , H04L2012/5672 , H04L2012/5679 , H04L2012/5681 , H04Q11/0478
摘要： The invention proposes a switching arrangement for transporting data packets from input ports of a switching device to output ports thereof. The data packets comprise a payload. The switching device is able to route the arriving data packets according to data packet destination information to at least one dedicated of the output ports. The switching arrangement comprises for each set of input ports in the switching device a set of output buffers. Such a set of input ports may comprise one or several input ports. The set of output buffers comprises for each set of output ports an output buffer for storing at least the payload of each data packet arriving at the corresponding input port, belonging to the set of input ports, at an address in at least those of the output buffers which pertain to the same set of output buffers, and which belong to the dedicated output ports. A set of output ports may comprise one or several output ports. For at least one of the output buffers a set of output queues is arranged which comprises for each output port an output queue, for storing therein, sorted according to the data packet destination information, the address of each payload stored in the corresponding output buffer. For the output queues which pertain to the same output port an arbiter controls a readout order of the stored addresses. For the output buffers which pertain to the same set of output ports a multiplexer multiplexes according to the readout order the stored payloads from the output buffers to the output ports.
摘要翻译：本发明提出了一种用于将数据分组从交换设备的输入端口传送到其输出端口的切换装置。数据分组包括有效载荷。交换设备能够根据数据分组目的地信息将到达的数据分组路由到至少一个专用的输出端口。开关装置包括用于开关装置中的每组输入端口的一组输出缓冲器。这样一组输入端口可以包括一个或多个输入端口。所述输出缓冲器组包括用于每组输出端口的输出缓冲器，用于至少存储属于所述一组输入端口的到达对应输入端口的每个数据分组的有效载荷，所述输入缓冲器至少在所述输出端口的地址处属于同一组输出缓冲区的属于专用输出端口的缓冲区。一组输出端口可以包括一个或多个输出端口。对于输出缓冲器中的至少一个，布置了一组输出队列，其包括针对每个输出端口的输出队列，用于存储其中根据数据分组目的地信息分类的输出队列，存储在相应输出缓冲器中的每个有效载荷的地址。对于与相同输出端口相关的输出队列，仲裁器控制存储地址的读出顺序。对于与同一组输出端口相关的输出缓冲器，复用器根据读出顺序将存储的有效载荷从输出缓冲器复用到输出端口。

3. 发明申请

WO2002076042A1 CACHE ENTRY SELECTION METHOD AND APPARATUS 审中-公开
标题翻译： CACHE入选选择方法和设备
公开(公告)号：WO2002076042A1
公开(公告)日：2002-09-26
申请号：PCT/IB2002/000822
申请日：2002-03-15
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , LUIJTEN, Ronald, P. , HERKERSDORF, Andreas
发明人： LUIJTEN, Ronald, P. , HERKERSDORF, Andreas
IPC分类号： H04L12/56
CPC分类号： H04L45/00 , H04L45/30 , H04L45/54 , H04L45/742 , H04L49/205 , H04L49/25
摘要： A method for selectively inserting cache entries into a cache memory is proposed in which incoming data packets are directed to output links according to address information. The method comprises the following steps: a) an evaluation step for evaluating for each incoming data packet classification information which is relevant to the type of traffic flow or to the traffic priority to which the data packet is associated; b) a selection step for selecting based on the result of the evaluation step whether for the data packet the cache entry is to be inserted into the cache memory; c) an entry step for inserting as the cache entry into the cache memory, in the case the result of the selection step is that the cache entry is to be inserted, for the data packet the address information and associated output link information.
摘要翻译：提出了一种将高速缓存条目选择性地插入到高速缓冲存储器中的方法，其中根据地址信息将输入数据分组引导到输出链路。该方法包括以下步骤：a）用于评估与业务流的类型相关的每个输入数据分组分类信息或数据分组所关联的业务优先级的评估步骤; b）选择步骤，用于基于评估步骤的结果来选择是否将高速缓存条目插入到高速缓冲存储器中的数据包; c）用于将所述高速缓存条目插入所述高速缓冲存储器中的入口步骤，在所述选择步骤的结果是所述高速缓存条目要被插入的情况下，对于所述数据包，所述地址信息和相关联的输出链接信息。

4. 发明申请

WO2011070506A2 COMPUTER-IMPLEMENTED METHOD OF PROCESSING RESOURCE MANAGEMENT 审中-公开
标题翻译：计算机实施资源管理方法
公开(公告)号：WO2011070506A2
公开(公告)日：2011-06-16
申请号：PCT/IB2010/055626
申请日：2010-12-07
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , HUNTER, Hillery C. , LUIJTEN, Ronald P. , STANLEY-MARBELL, Phillip
发明人： HUNTER, Hillery C. , LUIJTEN, Ronald P. , STANLEY-MARBELL, Phillip
IPC分类号： G06F9/48
CPC分类号： G06F9/4856 , G06F9/5033 , G06F2212/271
摘要： A computer-implemented method for managing processing resources of a computerized system having at least a first processor and a second processor, each of the processors operatively interconnected to a memory storing a set of data to be processed by a processor, the method comprising: monitoring data accessed by the first processor while executing; and if the second processor is at a shorter distance than the first processor from the monitored data, instructing to interrupt execution at the first processor and resume the execution at the second processor.
摘要翻译：一种用于管理具有至少第一处理器和第二处理器的计算机化系统的处理资源的计算机实现的方法，每个处理器可操作地互连到存储要由处理器处理的一组数据的存储器，所述方法包括：监视在执行时由第一处理器访问的数据; 并且如果所述第二处理器距所述监视数据的距离小于所述第一处理器，则指示中断所述第一处理器处的执行并在所述第二处理器处继续执行。

5. 发明申请

WO2007120209A3 METHOD AND SYSTEM TO REDUCE INTERCONNECT LATENCY 审中-公开
公开(公告)号：WO2007120209A3
公开(公告)日：2007-10-25
申请号：PCT/US2006/044213
申请日：2006-11-14
申请人： CORNING INCORPORATED , ABEL, Francois G. , BENNER, Alan F. , GRZYBOWSKI, Richard R. , HEMENWAY, Brewster R. Jr. , ILIADIS, Ilias , KRISHNAMURTHY, Rajaram , LUIJTEN, Ronald P. , MINKENBERG, Cyriel
发明人： ABEL, Francois G. , BENNER, Alan F. , GRZYBOWSKI, Richard R. , HEMENWAY, Brewster R. Jr. , ILIADIS, Ilias , KRISHNAMURTHY, Rajaram , LUIJTEN, Ronald P. , MINKENBERG, Cyriel
IPC分类号： H04L12/56
摘要： A method and system for reducing arbitration latency employs speculative transmission (STX) without prior arbitration in combination with routing fabric (306) scheduled arbitration. Packets are sent from source locations (321) to a routing fabric (306) through scheduled arbitration, and also through speculative arbitration, to non- contentiously allocate outputs that were not previously reserved in the routing fabric (306) to the speculatively transmitted packets.

6. 发明申请

WO2007120209A2 METHOD AND SYSTEM TO REDUCE INTERCONNECT LATENCY 审中-公开
标题翻译：减少互连延迟的方法和系统
公开(公告)号：WO2007120209A2
公开(公告)日：2007-10-25
申请号：PCT/US2006044213
申请日：2006-11-14
申请人： CORNING INC , ABEL FRANCOIS G , BENNER ALAN F , GRZYBOWSKI RICHARD R , HEMENWAY BREWSTER R JR , ILIADIS ILIAS , KRISHNAMURTHY RAJARAM , LUIJTEN RONALD P , MINKENBERG CYRIEL
发明人： ABEL FRANCOIS G , BENNER ALAN F , GRZYBOWSKI RICHARD R , HEMENWAY BREWSTER R JR , ILIADIS ILIAS , KRISHNAMURTHY RAJARAM , LUIJTEN RONALD P , MINKENBERG CYRIEL
CPC分类号： H04L45/00 , H04L12/417 , H04L43/087 , H04L45/62 , H04L47/50 , H04L47/58 , H04L49/254 , H04L49/3027 , H04L49/508
摘要： A method and system for reducing arbitration latency employs speculative transmission (STX) without prior arbitration in combination with routing fabric scheduled arbitration. Packets are sent from source locations to a routing fabric through scheduled arbitration, and also through speculative arbitration, to non- contentiously allocate outputs that were not previously reserved in the routing fabric to the speculatively transmitted packets.
摘要翻译：用于减少仲裁延迟的方法和系统使用推测传输（STX），而没有预先仲裁结合路由结构调度仲裁。数据包通过调度仲裁从源位置发送到路由结构，并通过推测仲裁，将非先前保留在路由结构中的输出非争用地分配给推测性传输的数据包。

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