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1. 发明申请

WO2014113027A1 HIGH-VOLTAGE VOLTAGE-SWITCHED CLASS-S AMPLIFIER 审中-公开
标题翻译：高压电压开关级放大器
公开(公告)号：WO2014113027A1
公开(公告)日：2014-07-24
申请号：PCT/US2013/022318
申请日：2013-01-18
申请人： LSI CORPORATION
发明人： LATURELL, Donald, R. , ABDELLI, Said, E. , KISS, Peter , MACDONALD, James, F. , WILSON, Ross, S.
IPC分类号： H03F3/04
CPC分类号： H03F3/2171 , H03F3/193 , H03F3/217 , H03F3/2175 , H03F3/2178 , H03F3/245 , H03F2200/451 , H03F2203/21136 , H03F2203/21178
摘要： A voltage-switched class-S amplifier circuit includes an output stage configured to receive at least one control signal and operative to generate an output signal as a function of the at least one control signal. The amplifier circuit further includes a driver circuit coupled with the output stage. The driver circuit is configured to receive an input bit stream signal and is operative to generate the control signal as a function of the input bit stream signal in such a manner that a common mode component is eliminated from the control signal.
摘要翻译：电压开关类S放大器电路包括输出级，其被配置为接收至少一个控制信号并且可操作以产生作为至少一个控制信号的函数的输出信号。放大器电路还包括与输出级耦合的驱动器电路。驱动器电路被配置为接收输入比特流信号，并且可操作以以从控制信号中消除共模分量的方式产生作为输入比特流信号的函数的控制信号。

2. 发明申请

WO2014142943A1 SINGLE-SIDEBAND TRANSMITTER USING CLASS-S AMPLIFIER 审中-公开
标题翻译：单级放大器单侧发射机
公开(公告)号：WO2014142943A1
公开(公告)日：2014-09-18
申请号：PCT/US2013/031892
申请日：2013-03-15
申请人： LSI CORPORATION
发明人： KISS, Peter , ABDELLI, Said, E. , LATURELL, Donald, R. , MACDONALD, James, F. , PINAULT, Steven, C. , WILSON, Ross, S.
IPC分类号： H03C1/52 , H04L27/00
CPC分类号： H04B1/0475 , H03C1/52 , H03C1/60 , H03F3/24 , H04B1/68 , H04B2001/0408 , H04L27/02 , H04L27/06 , H04L27/063
摘要： An SSB transmitter includes a digital-to-digital converter generating first and second real signal components as a function of a complex input signal supplied to the transmitter, and a digital Hilbert transformation module coupled with the digital-to-digital converter and operative to generate first and second transformed signals as a function of the first and second real signal components. The transmitter further includes first and second bit-stream generators operative to generate first and second analog signals as a function of the first and second transformed signals, respectively. The transmitter includes first and second amplifiers. The first amplifier is operative to generate a first amplified signal as a function of the first analog signal. The second amplifier is operative to generate a second amplified signal as a function of the second analog signal. An analog hybrid coupler is connected with the first and second amplifiers and operative to perform an analog Hilbert transformation.
摘要翻译： SSB发射机包括数字 - 数字转换器，其产生作为提供给发射机的复合输入信号的函数的第一和第二实信号分量;以及数字希尔伯特变换模块，与数字 - 数字转换器耦合并且可操作以产生第一和第二变换信号作为第一和第二实信号分量的函数。发射机还包括第一和第二比特流发生器，用于分别产生作为第一和第二变换信号的函数的第一和第二模拟信号。发射机包括第一和第二放大器。第一放大器用于产生作为第一模拟信号的函数的第一放大信号。第二放大器用于产生作为第二模拟信号的函数的第二放大信号。模拟混合耦合器与第一和第二放大器连接并且可操作以执行模拟希尔伯特变换。

3. 发明申请

WO2014113028A1 CASCADED VITERBI BITSTREAM GENERATOR 审中-公开
标题翻译： CASCADED VITERBI BITSTREAM发电机
公开(公告)号：WO2014113028A1
公开(公告)日：2014-07-24
申请号：PCT/US2013/022321
申请日：2013-01-18
申请人： LSI CORPORATION
发明人： KISS, Peter , ABDELLI, Said, E. , LATURELL, Donald, R. , MACDONALD, James, F. , WILSON, Ross, S.
IPC分类号： H03M13/03
CPC分类号： H04L1/0059 , G06F17/10 , H03M7/3022 , H03M13/23 , H03M13/41
摘要： A bitstream generator includes at least first and second bitstream generator stages connected in a cascaded arrangement. The first bitstream generator stage includes a first adder which receives an input signal and generates a first error signal indicative of a difference between the input signal and a first bitstream candidate representing a closest approximation to the input signal among multiple bitstream candidates generated by the first bitstream generator stage. The second bitstream generator stage includes a second adder which receives the first error signal and generates a second error signal indicative of a difference between the first error signal and a second bitstream candidate representing a closest approximation to the input signal among multiple bitstream candidates generated by the second bitstream generator stage. A third adder in the bitstream generator receives the first and second bitstream candidates and generates an output signal more closely approximating the input signal.
摘要翻译：比特流发生器至少包括以级联方式连接的第一和第二比特流发生器级。第一比特流发生器级包括第一加法器，其接收输入信号并产生第一误差信号，该第一误差信号指示输入信号和表示与由第一比特流产生的多个比特流候选中最接近输入信号的第一比特流候选之间的差异发电机阶段。第二比特流发生器级包括第二加法器，其接收第一误差信号并产生指示第一误差信号和第二比特流候选之间的差的第二误差信号，该第二误码信号表示与由第二比特流发生器阶段。比特流发生器中的第三加法器接收第一和第二比特流候选，并产生更近似于输入信号的输出信号。

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