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1. 发明申请

WO2017147886A1 METHOD FOR ROBUST PHASE-LOCKED LOOP DESIGN 审中-公开
标题翻译：鲁棒锁相环设计方法
公开(公告)号：WO2017147886A1
公开(公告)日：2017-09-08
申请号：PCT/CN2016/075533
申请日：2016-03-03
申请人： QUALCOMM INCORPORATED , YU, Hongchun , LIN, Weiran , LI, Shuguang , YIN, Guangming
发明人： YU, Hongchun , LIN, Weiran , LI, Shuguang , YIN, Guangming
IPC分类号： H03K7/00
CPC分类号： H03L7/0814 , H03K2005/00058 , H03L7/093 , H04L7/0331
摘要： Systems, methods, and apparatus (100) are disclosed that can improve robustness of digital phase locked loop (PLL) circuits. A method performed by a clock generation device includes generating a plurality of phase-shifted signals, each of the plurality of phase-shifted signals having a phase shift with respect to a base clock signal (202) that is unique within the plurality of phase-shifted signals, selecting a first phase-shifted signal as an output signal (222), generating a first phase control word ( 312) indicative of a second phase-shifted signal when the second signal has a closer phase relationship with a reference signal (204) than the first signal, refraining from selecting the second signal as the output signal (222) while either of the first signal and the second signal is in a first signaling state, and selecting as the output signal (222), the second signal when the first signal and the second signal are in a second signaling state.
摘要翻译：公开了可以提高数字锁相环（PLL）电路的鲁棒性的系统，方法和装置（100）。由时钟生成设备执行的方法包括：生成多个相移信号，多个相移信号中的每一个相对于在多个相移信号中唯一的基时钟信号（202）具有相移，选择第一相移信号作为输出信号（222）;当第二信号与参考信号（204）具有更接近的相位关系时，产生指示第二相移信号的第一相位控制字（312）），当所述第一信号和所述第二信号中的任一个处于第一信号状态时，避免选择所述第二信号作为所述输出信号（222），并且选择所述第二信号作为所述输出信号（222）第一信号和第二信号处于第二信令状态。

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