专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07585718B2 Method of manufacturing a carbon nano-tube transistor 失效
标题翻译：制造碳纳米管晶体管的方法
公开(公告)号：US07585718B2
公开(公告)日：2009-09-08
申请号：US11932994
申请日：2007-10-31
申请人： Hong Cho , Seung-Pil Chung , Hong Sik Yoon , Kyung-Rae Byun
发明人： Hong Cho , Seung-Pil Chung , Hong Sik Yoon , Kyung-Rae Byun
IPC分类号： H01L21/336 , H01L21/335
CPC分类号： H01L51/057 , B82Y10/00 , H01L51/0048 , Y10T29/49105
摘要： A multilayer insulating structure including a first stop layer, a first insulating layer and a second stop layer is formed on the first conductive structure. A second conductive structure and a second insulating layer are formed on the first conductive structure. The second insulating layer and the second conductive structure are etched to form a first hole and a second hole having a first radius. A spacer is formed on sidewalls of the first and second holes. The second stop layer and the first insulating layer are etched using the spacer as an etch mask to form a third hole having a second radius smaller than the first radius. A sacrificial filler is formed on the first stop layer to fill the third hole. After removing the spacer, the sacrificial filler is removed. The first stop layer is etched. A carbon nano-tube is grown from the first conductive structure.
摘要翻译：在第一导电结构上形成包括第一阻挡层，第一绝缘层和第二阻挡层的多层绝缘结构。在第一导电结构上形成第二导电结构和第二绝缘层。蚀刻第二绝缘层和第二导电结构以形成具有第一半径的第一孔和第二孔。间隔件形成在第一孔和第二孔的侧壁上。使用间隔物作为蚀刻掩模蚀刻第二阻挡层和第一绝缘层，以形成具有小于第一半径的第二半径的第三孔。在第一停止层上形成牺牲填料以填充第三孔。去除间隔物后，去除牺牲填料。第一个停止层被蚀刻。从第一导电结构生长碳纳米管。

2. 发明申请

US20080016675A1 Methods of Forming Magnetic Memory Devices Including Ferroelectric Spacers 有权
标题翻译：形成包含铁电隔离器的磁存储器件的方法
公开(公告)号：US20080016675A1
公开(公告)日：2008-01-24
申请号：US11776625
申请日：2007-07-12
申请人： Kyung-Rae Byun , Sung-Lae Cho
发明人： Kyung-Rae Byun , Sung-Lae Cho
IPC分类号： H01F7/06 , G11B5/127 , H05K3/10
CPC分类号： H01L43/12 , G11C11/16 , H01L27/228 , H01L43/08 , Y10T29/49043 , Y10T29/49044 , Y10T29/49046 , Y10T29/49048 , Y10T29/49052 , Y10T29/49155
摘要： A magnetic memory device may include a digit line on a substrate, a first insulating layer on the digit line, and a magnetic tunnel junction memory cell on the first insulating layer so that the first insulating layer is between the digit line and the magnetic tunnel junction memory cell. A second insulating layer may be provided on the magnetic tunnel junction memory cell, wherein the second insulating layer has a hole therein exposing portions of the magnetic tunnel junction memory cell. A bit line may be provided on the second insulating layer and on portions of the magnetic tunnel junction memory cell exposed by the hole in the second insulating layer, and ferromagnetic spacers may be provided on sidewalls of at least one of the digit line and/or the bit line. Related methods are also discussed.
摘要翻译：磁存储器件可以包括衬底上的数字线，数字线上的第一绝缘层和第一绝缘层上的磁性隧道结存储单元，使得第一绝缘层位于数字线和磁性隧道结之间记忆单元第二绝缘层可以设置在磁性隧道结存储单元上，其中第二绝缘层在其中具有一个孔，暴露出磁性隧道结存储单元的部分。位线可以设置在第二绝缘层上以及在由第二绝缘层中的孔暴露的磁性隧道结存储单元的部分上，并且铁磁间隔物可以设置在数字线和/或其中的至少一个的侧壁上位线。还讨论了相关方法。

3. 发明申请

US20060273366A1 Methods of manufacturing ferroelectric capacitors and semiconductor devices 审中-公开
标题翻译：制造铁电电容器和半导体器件的方法
公开(公告)号：US20060273366A1
公开(公告)日：2006-12-07
申请号：US11447545
申请日：2006-06-06
申请人： Hwa-Young Ko , Suk-Ho Joo , Byoung-Jae Bae , Hee-Seok Kim , Kyung-Rae Byun , Jin-Hwan Ham
发明人： Hwa-Young Ko , Suk-Ho Joo , Byoung-Jae Bae , Hee-Seok Kim , Kyung-Rae Byun , Jin-Hwan Ham
IPC分类号： H01L29/94
CPC分类号： H01L28/55 , H01L21/32139 , H01L27/11502 , H01L27/11507 , H01L28/65
摘要： In a method of manufacturing a ferroelectric capacitor, a lower electrode layer is formed on a substrate. The lower electrode layer includes at least one lower electrode film. A ferroelectric layer is formed on the lower electrode layer, and then an upper electrode layer is formed on the ferroelectric layer. A hard mask structure is formed on the upper electrode layer. The hard mask structure includes a first hard mask and a second hard mask. An upper electrode, a ferroelectric layer pattern and a lower electrode are formed by partially etching the upper electrode layer, the ferroelectric layer and the lower electrode layer using the hard mask structure. The hard mask structure may prevent damage to the ferroelectric layer and may enlarge an effective area of the ferroelectric capacitor so that the ferroelectric capacitor may have enhanced electrical and ferroelectric characteristics.
摘要翻译：在制造铁电电容器的方法中，在基板上形成下电极层。下电极层包括至少一个下电极膜。在下电极层上形成铁电体层，在铁电层上形成上电极层。在上电极层上形成硬掩模结构。硬掩模结构包括第一硬掩模和第二硬掩模。通过使用硬掩模结构部分蚀刻上电极层，铁电层和下电极层，形成上电极，铁电层图案和下电极。硬掩模结构可以防止对铁电层的损坏，并且可以增加铁电电容器的有效面积，使得铁电电容器可以具有增强的电和铁电特性。

4. 发明申请

US20060263289A1 METAL OXIDE RESISTIVE MEMORY AND METHOD OF FABRICATING THE SAME 审中-公开
公开(公告)号：US20060263289A1
公开(公告)日：2006-11-23
申请号：US11419986
申请日：2006-05-23
申请人： Jang-Eun HEO , Moon-Sook LEE , Young-Moon CHOI , In-Gyu BAEK , Yoon-Ho SON , Suk-Hun CHOI , Kyung-Rae BYUN
发明人： Jang-Eun HEO , Moon-Sook LEE , Young-Moon CHOI , In-Gyu BAEK , Yoon-Ho SON , Suk-Hun CHOI , Kyung-Rae BYUN
IPC分类号： D01F9/12
CPC分类号： G11C13/025 , B82Y10/00 , G11C13/0002 , G11C2213/35 , G11C2213/79 , H01L27/2436 , H01L45/04 , H01L45/122 , H01L45/1233 , H01L45/1253 , H01L45/146 , H01L45/1675
摘要： Disclosed is a metal-metal oxide resistive memory device including a lower conductive layer pattern disposed in a substrate. An insulation layer is formed over the substrate, including a contact hole to partially expose the upper surface of the lower conductive layer pattern. The contact hole is filled with a carbon nanotube grown from the lower conductive layer pattern. An upper electrode and a transition-metal oxide layer made of a 2-components material are formed over the carbon nanotube and the insulation layer. The metal-metal oxide resistive memory device is adaptable to high integration and operable with relatively small power consumption by increasing the resistance therein.

5. 发明申请

US20060022237A1 Magnetic memory devices including ferroelectric spacers and related methods 审中-公开
标题翻译：包括铁电间隔物和相关方法的磁存储器件
公开(公告)号：US20060022237A1
公开(公告)日：2006-02-02
申请号：US11093206
申请日：2005-03-29
申请人： Kyung-Rae Byun , Sung-Lae Cho
发明人： Kyung-Rae Byun , Sung-Lae Cho
IPC分类号： H01L29/94
CPC分类号： H01L43/12 , G11C11/16 , H01L27/228 , H01L43/08 , Y10T29/49043 , Y10T29/49044 , Y10T29/49046 , Y10T29/49048 , Y10T29/49052 , Y10T29/49155
摘要： A magnetic memory device may include a digit line on a substrate, a first insulating layer on the digit line, and a magnetic tunnel junction memory cell on the first insulating layer so that the first insulating layer is between the digit line and the magnetic tunnel junction memory cell. A second insulating layer may be provided on the magnetic tunnel junction memory cell, wherein the second insulating layer has a hole therein exposing portions of the magnetic tunnel junction memory cell. A bit line may be provided on the second insulating layer and on portions of the magnetic tunnel junction memory cell exposed by the hole in the second insulating layer, and ferromagnetic spacers may be provided on sidewalls of at least one of the digit line and/or the bit line. Related methods are also discussed.
摘要翻译：磁存储器件可以包括衬底上的数字线，数字线上的第一绝缘层和第一绝缘层上的磁性隧道结存储单元，使得第一绝缘层位于数字线和磁性隧道结之间记忆单元第二绝缘层可以设置在磁性隧道结存储单元上，其中第二绝缘层在其中具有一个孔，暴露出磁性隧道结存储单元的部分。位线可以设置在第二绝缘层上以及在由第二绝缘层中的孔暴露的磁性隧道结存储单元的部分上，并且铁磁间隔物可以设置在数字线和/或其中的至少一个的侧壁上位线。还讨论了相关方法。

6. 发明授权

US09679943B2 Semiconductor device 有权
公开(公告)号：US09679943B2
公开(公告)日：2017-06-13
申请号：US14710740
申请日：2015-05-13
申请人： Jong Chul Park , Shin Jae Kang , Shin Kwon , Kyung Rae Byun
发明人： Jong Chul Park , Shin Jae Kang , Shin Kwon , Kyung Rae Byun
IPC分类号： H01L43/08 , H01L27/22 , G11C11/16 , H01L43/10
CPC分类号： H01L27/228 , G11C11/161 , H01L43/10
摘要： A semiconductor device may include a first magnetic layer including a plurality of first regions configuring a plurality of memory cells and spaced apart from each other on a substrate, and a second region encompassing the plurality of first regions and electrically isolated from the first regions, a tunnel barrier layer disposed on the first magnetic layer, and a second magnetic layer disposed on the tunnel barrier layer.

7. 发明授权

US09634240B2 Magnetic memory devices 有权
公开(公告)号：US09634240B2
公开(公告)日：2017-04-25
申请号：US14567932
申请日：2014-12-11
申请人： Jongchul Park , Byoungjae Bae , Shin-Jae Kang , Eunsun Noh , Kyung Rae Byun
发明人： Jongchul Park , Byoungjae Bae , Shin-Jae Kang , Eunsun Noh , Kyung Rae Byun
IPC分类号： H01L43/08 , H01L43/02 , H01L43/12 , H01L27/22
CPC分类号： H01L43/08 , G11C11/161 , H01L27/228 , H01L43/02 , H01L43/12
摘要： Magnetic memory devices include a plurality of first magnetic patterns on a substrate so as to be spaced apart from each other, a first insulating pattern between the first magnetic patterns to define the first magnetic patterns, and a tunnel barrier layer covering the first magnetic patterns and the first insulating pattern. The first insulating pattern includes a first magnetic element, and the first magnetic element is the same as a second magnetic element constituting the first magnetic patterns.

8. 发明申请

US20160104745A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20160104745A1
公开(公告)日：2016-04-14
申请号：US14710740
申请日：2015-05-13
申请人： Jong Chul PARK , Shin Jae KANG , Shin KWON , Kyung Rae BYUN
发明人： Jong Chul PARK , Shin Jae KANG , Shin KWON , Kyung Rae BYUN
IPC分类号： H01L27/22 , H01L43/08 , G11C11/16 , H01L43/02
CPC分类号： H01L27/228 , G11C11/161 , H01L43/10
摘要： A semiconductor device may include a first magnetic layer including a plurality of first regions configuring a plurality of memory cells and spaced apart from each other on a substrate, and a second region encompassing the plurality of first regions and electrically isolated from the first regions, a tunnel barrier layer disposed on the first magnetic layer, and a second magnetic layer disposed on the tunnel barrier layer.
摘要翻译：半导体器件可以包括第一磁性层，其包括构成多个存储器单元并且在衬底上彼此间隔开的多个第一区域，以及包围多个第一区域并与第一区域电隔离的第二区域，设置在第一磁性层上的隧道势垒层，以及设置在隧道势垒层上的第二磁性层。

9. 发明申请

US20150287907A1 MAGNETIC MEMORY DEVICES 有权
标题翻译：磁记忆装置
公开(公告)号：US20150287907A1
公开(公告)日：2015-10-08
申请号：US14567932
申请日：2014-12-11
申请人： Jongchul PARK , Byoungjae BAE , Shin-Jae KANG , Eunsun NOH , Kyung Rae BYUN
发明人： Jongchul PARK , Byoungjae BAE , Shin-Jae KANG , Eunsun NOH , Kyung Rae BYUN
IPC分类号： H01L43/08 , H01L43/02
CPC分类号： H01L43/08 , G11C11/161 , H01L27/228 , H01L43/02 , H01L43/12
摘要： Magnetic memory devices include a plurality of first magnetic patterns on a substrate so as to be spaced apart from each other, a first insulating pattern between the first magnetic patterns to define the first magnetic patterns, and a tunnel barrier layer covering the first magnetic patterns and the first insulating pattern. The first insulating pattern includes a first magnetic element, and the first magnetic element is the same as a second magnetic element constituting the first magnetic patterns.
摘要翻译：磁存储器件包括在基板上彼此间隔开的多个第一磁性图案，第一磁性图案之间的第一绝缘图案，以限定第一磁性图案，以及覆盖第一磁性图案的隧道势垒层和第一绝缘图案。第一绝缘图案包括第一磁性元件，第一磁性元件与构成第一磁性图案的第二磁性元件相同。

10. 发明申请

US20090146304A1 CARBON NANOTUBE INTEGRATED CIRCUIT DEVICES AND METHODS OF FABRICATION THEREFOR USING PROTECTED CATALYST LAYERS 审中-公开
标题翻译：碳纳米管集成电路器件及其使用受保护的催化层的制造方法
公开(公告)号：US20090146304A1
公开(公告)日：2009-06-11
申请号：US11924308
申请日：2007-10-25
申请人： Yoon-ho Son , Sun-woo Lee , Young-moon Choi , Seong-ho Moon , Hong-sik Yoon , Suk-hun Choi , Kyung-rae Byun
发明人： Yoon-ho Son , Sun-woo Lee , Young-moon Choi , Seong-ho Moon , Hong-sik Yoon , Suk-hun Choi , Kyung-rae Byun
IPC分类号： H01L23/522 , H01L21/768
CPC分类号： H01L21/76879 , H01L21/76834 , H01L21/76849 , H01L21/7685 , H01L21/76876 , H01L23/5226 , H01L23/53276 , H01L2221/1094 , H01L2924/0002 , H01L2924/00
摘要： A method of fabricating an integrated circuit device is provided. The method includes sequentially forming a lower interconnection layer, a catalyst layer, and a buffer layer on a semiconductor substrate, forming an interlayer dielectric layer to cover the buffer layer, forming a contact hole through the interlayer dielectric layer so that a top surface of the buffer layer may be partially exposed, removing a portion of the buffer layer exposed by the contact hole so that a top surface of the catalyst layer may be exposed, and growing carbon nanotubes from a portion of the catalyst layer exposed by the contact hole so that the contact hole may be filled with the carbon nanotubes.
摘要翻译：提供一种制造集成电路器件的方法。该方法包括在半导体衬底上依次形成下互连层，催化剂层和缓冲层，形成覆盖缓冲层的层间电介质层，形成穿过层间电介质层的接触孔，缓冲层可以部分地暴露，去除由接触孔暴露的缓冲层的一部分，使得催化剂层的顶表面可能被暴露，并且从催化剂层的由接触孔暴露的部分生长碳纳米管，使得可以用碳纳米管填充接触孔。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式