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    • 1. 发明授权
    • Coherency coverage of data across multiple packets varying in sizes
    • 跨多个数据包的数据的一致性覆盖范围大小不等
    • US06850999B1
    • 2005-02-01
    • US10306009
    • 2002-11-27
    • Kwok Ken MakXiaoming Sun
    • Kwok Ken MakXiaoming Sun
    • G06F12/04G06F13/18H04L12/56
    • H04L49/901H04L49/90
    • A coherency resolution technique enables efficient resolution of data coherency for packet data associated with a service queue of an intermediate network node. The packet data is enqueued on a write buffer prior to being stored on an external packet memory of a packet memory system. The packet data may be interspersed among other packets of data from different service queues, wherein the packets are of differing sizes. In response to a read request for the packet data, a coherency operation is performed by coherency resolution logic on the data in the write buffer to determine if any of its enqueued data can be used to service the request.
    • 一致性解析技术能够有效地解决与中间网络节点的服务队列相关联的分组数据的数据一致性。 分组数据在被存储在分组存储器系统的外部分组存储器之前在写入缓冲器上排队。 分组数据可以散布在来自不同服务队列的其他数据分组之中,其中分组具有不同的大小。 响应于对分组数据的读取请求,通过写入缓冲器中的数据的相关性分辨率逻辑来执行一致性操作,以确定是否可以使用其任何入队数据来服务请求。
    • 2. 发明授权
    • System and method for operating a packet buffer in an intermediate node
    • 用于在中间节点中操作分组缓冲器的系统和方法
    • US08180966B2
    • 2012-05-15
    • US11090734
    • 2005-03-25
    • Kenneth M. KeyKwok Ken MakXiaoming Sun
    • Kenneth M. KeyKwok Ken MakXiaoming Sun
    • G06F12/02
    • H04L29/06H04L49/90H04L69/329
    • A technique implements a novel high-speed high-density packet buffer utilizing a combination of high-speed and low-speed memory devices. The novel packet buffer is organized as a plurality of FIFO queues where each FIFO queue is associated with a particular input or output line. Each queue comprises a high-speed cache portion that resides in high-speed memory and a low-speed high-density portion that resides in low-speed high-density memory. The high-speed cache portion contains FIFO data that contains head and/or tail associated with the novel FIFO queue. The low-speed high-density portion contains FIFO data that is not contained in the high-speed cache portion.
    • 一种技术实现了一种利用高速和低速存储器件组合的新型高速高密度分组缓冲器。 新颖的分组缓冲器被组织为多个FIFO队列,其中每个FIFO队列与特定输入或输出线相关联。 每个队列包括位于高速存储器中的高速缓存部分和位于低速高密度存储器中的低速高密度部分。 高速缓存部分包含FIFO数据,其包含与新颖的FIFO队列相关联的头部和/或尾部。 低速高密度部分包含不包含在高速缓存部分中的FIFO数据。
    • 3. 发明授权
    • System and method for operating a packet buffer
    • 用于操作分组缓冲区的系统和方法
    • US06892285B1
    • 2005-05-10
    • US10135603
    • 2002-04-30
    • Kenneth M. KeyKwok Ken MakXiaoming Sun
    • Kenneth M. KeyKwok Ken MakXiaoming Sun
    • H04L12/56H04L29/06H04L29/08G06F12/00
    • H04L29/06H04L49/90H04L69/329
    • A technique for implementing a novel high-speed high-density packet buffer utilizing a combination of high-speed and low-speed memory devices. The novel packet buffer is organized as a plurality of first-in-first-out (FIFO) queues where each FIFO queue is associated with a particular input or output line. Each queue comprises a high-speed cache portion that resides in high-speed memory and a low-speed high-density portion that resides in low-speed high-density memory. Each high-speed cache portion contains FIFO data that contains head and/or tail information associated with a corresponding FIFO queue. The low-speed high-density portion contains FIFO data that is not contained in the high-speed cache portion. A queue identifier (QID) directory refills the high-speed portion of one or more queues with data from a corresponding low-speed portion. Queue head start and end offsets are used to determine whether a corresponding queue is empty.
    • 一种利用高速和低速存储器件组合实现新型高速高密度分组缓冲器的技术。 新颖的分组缓冲器被组织为多个先进先出(FIFO)队列,其中每个FIFO队列与特定的输入或输出线相关联。 每个队列包括位于高速存储器中的高速缓存部分和位于低速高密度存储器中的低速高密度部分。 每个高速缓存部分包含FIFO数据,其中包含与对应的FIFO队列相关联的头部和/或尾部信息。 低速高密度部分包含不包含在高速缓存部分中的FIFO数据。 队列标识符(QID)目录使用来自相应的低速部分的数据来重新填充一个或多个队列的高速部分。 队列头开始和结束偏移量用于确定对应的队列是否为空。
    • 7. 发明授权
    • System and method for maintaining cache coherency using path directories
    • 使用路径目录维护高速缓存一致性的系统和方法
    • US5900015A
    • 1999-05-04
    • US694894
    • 1996-08-09
    • Lorraine Maria Paola HergerKwok-Ken MakKenneth Blair OcheltreeTu-Chih TsaiMichael Edward Wazlowski
    • Lorraine Maria Paola HergerKwok-Ken MakKenneth Blair OcheltreeTu-Chih TsaiMichael Edward Wazlowski
    • G06F12/08G06F13/00
    • G06F12/0824G06F12/0813
    • A method of maintaining cache coherency in a computer system including two or more processors sharing information, the processors coupled by two or more interconnects to a memory such that the processors are not directly coupled to the same is disclosed interconnect is disclosed. The method of maintaining cache coherency includes the steps of: accessing and sharing, by a first processor and a second processor, information from the memory and setting path indicators in directories associated with at least two of the interconnects on a respective first and second access path to the memory, and storing the information in respective associated first and second caches; and writing a new value to the information, by a writing processor sharing the information, the writing step including the steps of: invalidating other copies of the information via the path indicators; acquiring exclusive access to the information by changing the path indicators to an exclusive state; and writing the new value to the information, in response to the acquiring step.
    • 公开了一种在包括共享信息的两个或多个处理器共享信息的计算机系统中维持高速缓存一致性的方法,将两个或多个互连器耦合到存储器,使得处理器不直接耦合到存储器的处理器。 维护高速缓存一致性的方法包括以下步骤:由第一处理器和第二处理器访问和共享来自存储器的信息,并且在相应的第一和第二访问路径上与至少两个互连相关联的目录中设置路径指示符 并将信息存储在相关联的第一和第二高速缓存中; 并且通过共享所述信息的写入处理器向所述信息写入新的值,所述写入步骤包括以下步骤:通过所述路径指示器使所述信息的其他副本无效; 通过将路径指示器更改为独占状态来获取对信息的独占访问; 并且响应于获取步骤将新的值写入信息。
    • 8. 发明授权
    • Synchronization technique for high speed memory subsystem
    • 高速存储器子系统同步技术
    • US07469328B1
    • 2008-12-23
    • US10359985
    • 2003-02-06
    • Kwok Ken MakXiaoming Sun
    • Kwok Ken MakXiaoming Sun
    • G06F13/28G06F12/12
    • G06F13/1689
    • A technique synchronizes data retrieved from memory devices at a memory controller of a high-speed memory subsystem. Each memory device is organized into a plurality of data groupings. The memory controller stores (via one or more write operations) a known synchronization (sync) pattern at each data grouping on the memory devices and then retrieves (via one or more read operations) that sync pattern from the groupings. Synchronization logic located at a local clock boundary of the memory controller is configured to recognize the retrieved sync pattern and “automatically” synchronize all pieces of data retrieved from the data groupings, even though there may be substantial skew between the groupings.
    • 一种技术使从高速存储器子系统的存储器控​​制器中的存储器件获得的数据同步。 每个存储器件被组织成多个数据组。 存储器控制器在存储器设备上的每个数据分组处存储(经由一个或多个写入操作)已知的同步(同步)模式,然后从分组检索(经由一个或多个读取操作)同步模式。 位于存储器控制器的本地时钟边界的同步逻辑被配置为识别所检索的同步模式,并且“自动”同步从数据分组检索的所有数据片段,即使分组之间可能存在实质性的偏斜。
    • 9. 发明授权
    • Method and apparatus for high integrity hardware memory compression
    • 用于高完整性硬件存储器压缩的方法和装置
    • US06519733B1
    • 2003-02-11
    • US09511849
    • 2000-02-23
    • David HarKwok-Ken MakCharles O. SchulzT. Basil Smith, IIIR. Brett Tremaine
    • David HarKwok-Ken MakCharles O. SchulzT. Basil Smith, IIIR. Brett Tremaine
    • H03M1300
    • G06F11/1004G06F12/08G06F2212/401H03M7/30
    • In a processing system having a main memory, wherein information is stored in a compressed format for the purpose of gaining additional storage through compression efficiencies, a method and apparatus for providing compressed data integrity verification to insure detection of nearly any data corruption resulting from an anomaly anywhere in the logical processing or storage of compressed information. A cyclic redundancy code (CRC) is computed over a compressed data block as the data enters the compressor hardware, and the CRC is appended to the compressor output block before it is stored into the main memory. Subsequent read access results in comparing the CRC against a recomputation of the CRC as the block is uncompressed from the main memory. Any CRC miscompare implies an uncorrectable data error condition that may be used to interrupt the system operation.
    • 在具有主存储器的处理系统中,其中以压缩格式存储信息以通过压缩效率获得额外的存储,提供压缩数据完整性验证的方法和装置,以确保几乎任何由异常引起的数据损坏的检测 任何地方在逻辑处理或存储压缩信息。 当数据进入压缩器硬件时,在压缩数据块上计算循环冗余码(CRC),并且在存储到主存储器之前将CRC附加到压缩器输出块。 随后的读取访问导致在块与主存储器未压缩时比较CRC与CRC的重新计算。 任何CRC错误比较意味着可能用于中断系统操作的不可校正数据错误条件。