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1. 发明申请

US20130058319A1 Network Processor 有权
标题翻译：网络处理器
公开(公告)号：US20130058319A1
公开(公告)日：2013-03-07
申请号：US13528844
申请日：2012-06-21
申请人： Kuo-Yen Fan , Kuo-Cheng Lu
发明人： Kuo-Yen Fan , Kuo-Cheng Lu
IPC分类号： H04L12/66 , H04W40/00 , H04W84/12 , H04L29/10
CPC分类号： H04L49/15 , H04W88/16 , H04W92/02
摘要： The present invention discloses a network processor for a broadband gateway. The network processor includes a host processor; a plurality of networking interfaces, corresponding to a plurality of networking technologies, respectively; and a network address translation (NAT) engine, for accelerating packet processing from a first networking interface to a second networking interface.
摘要翻译：本发明公开了一种用于宽带网关的网络处理器。网络处理器包括主机处理器; 分别对应于多个联网技术的多个网络接口; 以及网络地址转换（NAT）引擎，用于加速从第一网络接口到第二网络接口的分组处理。

2. 发明授权

US06535516B1 Shared memory based network switch and the network constructed with the same 有权
标题翻译：基于共享内存的网络交换机和网络构造相同
公开(公告)号：US06535516B1
公开(公告)日：2003-03-18
申请号：US09350471
申请日：1999-07-09
申请人： Kuo-Cheng Leu , Shu-Wei Wang , Kuo-Yen Fan , Hai-Yang Huang
发明人： Kuo-Cheng Leu , Shu-Wei Wang , Kuo-Yen Fan , Hai-Yang Huang
IPC分类号： H04L1228
CPC分类号： H04L49/103 , H04L49/3027 , H04L49/351 , H04L49/90
摘要： A shared memory based network having a transferring network switch and a receiving network switch. In this network, each network switch has a stack, queues corresponding to output ports and a dared control port. The stack stores available buffer addresses of the shared memory. Each of the queues stores to-be-accessed buffer addresses of the corresponding output port. The shared control port is driven to indicate states of the shared memory based network, so that th stack of the transferring network switch is identical with the stack of the receiving network switch. The shared memory can be read by all output ports of both the transferring network switch and the receiving network switch according to their corresponding queues.
摘要翻译：一种基于共享内存的网络，具有传送网络交换机和接收网络交换机。在这个网络中，每个网络交换机都有一个堆叠，对应于输出端口的队列和一个敢死的控制端口。堆栈存储共享存储器的可用缓冲区地址。每个队列存储相应输出端口的被访问缓冲区地址。驱动共享控制端口以指示基于共享存储器的网络的状态，使得传输网络交换机的堆叠与接收网络交换机的堆叠相同。共享内存可以根据传输网络交换机和接收网络交换机的所有输出端口根据其相应的队列进行读取。

3. 发明授权

US6092137A Fair data bus arbitration system which assigns adjustable priority values to competing sources 失效
标题翻译：公平的数据总线仲裁系统，为竞争源分配可调优先级值
公开(公告)号：US6092137A
公开(公告)日：2000-07-18
申请号：US978580
申请日：1997-11-26
申请人： Paul Huang , Huan-Pin Tseng , Yao-Tzung Wang , Tai-Chung Chang , Kuo-Yen Fan
发明人： Paul Huang , Huan-Pin Tseng , Yao-Tzung Wang , Tai-Chung Chang , Kuo-Yen Fan
IPC分类号： G06F13/364 , G06F13/00
CPC分类号： G06F13/364
摘要： A scheme for arbitrating access to a data bus shared among a plurality of competing sources is provided. Each competing source is assigned an adjustable priority weighting value (PWV) which is initially set to an initial value based on the bandwidth requirements of the competing source. During arbitration, the PWVs of those competing sources requesting access to the bus are compared, and the competing source with the smallest PWV is granted access. The PWV of the competing source which was granted access to the bus is reset to its initial value and the PWV of each competing source which requested, but was denied, access is reduced by one for subsequent comparisons. The arbitration scheme of the present invention is further applied to two-level arbitration. Each competing source is classified into a competing source group, and the requests from the grouped competing sources are processed by first level arbitration. First level arbitration passes one competing source for each group to a second level arbiter. The second level arbiter compares the PWVs of the competing sources resulting from first level arbitration to determine the competing source with the smallest PWV, and adjusts the PWVs after access to the bus has been granted.
摘要翻译：提供了一种用于仲裁访问多个竞争源之间共享的数据总线的方案。每个竞争源被分配有可调优先权重值（PWV），其基于竞争源的带宽需求被初始设置为初始值。在仲裁期间，比较了请求访问总线的竞争源的PWV，允许访问具有最小PWV的竞争源。允许访问总线的竞争源的PWV重置为其初始值，并且请求但被拒绝访问的每个竞争源的PWV减少一个用于随后的比较。本发明的仲裁方案进一步适用于两级仲裁。每个竞争源被分类为竞争源组，来自分组竞争源的请求通过一级仲裁处理。第一级仲裁将每个组的一个竞争源传递给第二级仲裁器。第二级仲裁者比较由一级仲裁产生的竞争源的PWV，以确定具有最小PWV的竞争源，并且在访问总线之后调整PWV。

4. 发明授权

US09246846B2 Network processor 有权
标题翻译：网络处理器
公开(公告)号：US09246846B2
公开(公告)日：2016-01-26
申请号：US13528844
申请日：2012-06-21
申请人： Kuo-Yen Fan , Kuo-Cheng Lu
发明人： Kuo-Yen Fan , Kuo-Cheng Lu
IPC分类号： H04W4/00 , G06F15/16 , H04L12/933 , H04W88/16 , H04W92/02
CPC分类号： H04L49/15 , H04W88/16 , H04W92/02
摘要： The present invention discloses a network processor for a broadband gateway. The network processor includes a host processor; a plurality of networking interfaces, corresponding to a plurality of networking technologies, respectively; and a network address translation (NAT) engine, for accelerating packet processing from a first networking interface to a second networking interface.
摘要翻译：本发明公开了一种用于宽带网关的网络处理器。网络处理器包括主机处理器; 分别对应于多个联网技术的多个网络接口; 以及网络地址转换（NAT）引擎，用于加速从第一网络接口到第二网络接口的分组处理。

5. 发明申请

US20050004966A1 System and method for efficient VLSI architecture of finite fields 审中-公开
标题翻译：有限域高效VLSI架构的系统与方法
公开(公告)号：US20050004966A1
公开(公告)日：2005-01-06
申请号：US10883669
申请日：2004-07-06
申请人： Kuo-Yen Fan
发明人： Kuo-Yen Fan
IPC分类号： G06F7/00 , G06F7/52 , G06F7/552 , G06F7/72
CPC分类号： G06F7/724
摘要： An architecture according to the present invention performs arithmetic operations on a composite field over dual basis. The ground field arithmetic is performed under dual basis. Therefore, the proposed architectures has the advantages of both composite field and dual basis processing, area efficiency and timing efficiency. Moreover, if the ground field GF(2n) arithmetic is implemented by bit-serial operation, the overall throughput of the composite field GF((2n)k) arithmetic will be twice than the one implemented in the finite field GF(2m)m=nk).
摘要翻译：根据本发明的架构在双重基础上对复合场进行算术运算。地面场算术是在双重基础上进行的。因此，所提出的架构具有复合场和双基处理，面积效率和时序效率两方面的优点。此外，如果通过比特串行操作来实现地面场GF（2n）运算，则复合场GF（（2n））算术的总体吞吐量将是实现在有限域GF（2m）m = nk）。

6. 发明授权

US06363075B1 Shared buffer management mechanism and method using multiple linked lists in a high speed packet switching system 失效
标题翻译：在高速分组交换系统中使用多个链表的共享缓冲器管理机制和方法
公开(公告)号：US06363075B1
公开(公告)日：2002-03-26
申请号：US09012225
申请日：1998-01-23
申请人： Paul Huang , Huan-Pin Tseng , Yao-Tzung Wang , Tai-Chung Chang , Kuo-Yen Fan
发明人： Paul Huang , Huan-Pin Tseng , Yao-Tzung Wang , Tai-Chung Chang , Kuo-Yen Fan
IPC分类号： H04L1256
CPC分类号： H04L49/9036 , H04L29/06 , H04L49/90
摘要： A shared memory management mechanism and method for a high-speed network releases network packets efficiently and maintains the requirement of First In First Out. A series of linked lists including a linked list for each output queue and a linked list of used broadcast packets aids a buffer manager in efficiently managing the buffers in the shared memory. The linked lists include a special data format that encodes the broadcast status, links, and whether the next entry in the list is for unicast or broadcast frames. A scanning procedure scans the broadcast status to efficiently release the broadcast frame buffers. A dynamic scanning procedure consumes less bandwidth than the scanning procedure to efficiently release the broadcast frame buffers.
摘要翻译：高速网络的共享内存管理机制和方法有效发布网络报文，保持先进先出的要求。一系列链接列表，包括每个输出队列的链接列表和已使用的广播数据包的链接列表，有助于缓冲管理器有效地管理共享内存中的缓冲区。链表包括编码广播状态，链接以及列表中的下一个条目是单播还是广播帧的特殊数据格式。扫描过程扫描广播状态以有效地释放广播帧缓冲器。动态扫描过程比扫描过程消耗更少的带宽以有效地释放广播帧缓冲器。

7. 发明申请

US20120281714A1 PACKET PROCESSING ACCELERATOR AND METHOD THEREOF 审中-公开
标题翻译：分组处理加速器及其方法
公开(公告)号：US20120281714A1
公开(公告)日：2012-11-08
申请号：US13227927
申请日：2011-09-08
申请人： Shang Pin Chang , Kuo Yen Fan , Chung Chi Lo , Shuenn Ren Liu
发明人： Shang Pin Chang , Kuo Yen Fan , Chung Chi Lo , Shuenn Ren Liu
IPC分类号： H04J99/00
CPC分类号： H04L49/10 , H04L47/2441 , H04L49/3009
摘要： A packet processing accelerator comprises a programmable packet classification module, a programmable flow control module, and a programmable packet header modification module. The programmable packet classification module is configured to receive a data packet and generate a start location of each protocol header of the data packet and a first index. The first index indicates classification of the data packet. The programmable flow control module is configured to generate a code of an output port and an action code according to the start location of each protocol header of the data packet and the first index. The programmable packet header modification module is configured to modify content of a plurality of protocol headers of the data packet according to the action code and to send the modified data packet to an output port according to the code of the output port.
摘要翻译：分组处理加速器包括可编程分组分类模块，可编程流控制模块和可编程分组报头修改模块。可编程分组分类模块被配置为接收数据分组并且生成数据分组的每个协议报头的起始位置和第一索引。第一个索引表示数据包的分类。可编程流控制模块被配置为根据数据分组的每个协议报头和第一索引的开始位置生成输出端口和动作代码的代码。可编程分组报头修改模块被配置为根据动作代码修改数据分组的多个协议报头的内容，并根据输出端口的代码将修改的数据分组发送到输出端口。

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