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1. 发明授权

US06598160B1 IPL system applied to a multiprocessor system 失效
标题翻译： IPL系统应用于多处理器系统
公开(公告)号：US06598160B1
公开(公告)日：2003-07-22
申请号：US09607127
申请日：2000-06-29
申请人： Kosei Mano
发明人： Kosei Mano
IPC分类号： G06F15177
CPC分类号： G06F9/4416
摘要： An IPL system according to the present invention includes a file server, a dividing unit and a decision unit. The file server stores system data consisting of programs and data. The dividing unit is operatively connected to the file server, divides the system data into functional units, and prepares functional processors each structured by gathering the functional units. The decision unit is operatively connected to the file server and determines the functional processors to be transferred to each of the plurality of processors, in accordance with contents of operation data which are different from each other in each of the plurality of processors. According to the present invention, it is possible to realize an effective IPL of the processor by selectively using functional processors consisting of system data functional processors and operation data functional processors, in accordance with the different functions in each processor.
摘要翻译：根据本发明的IPL系统包括文件服务器，分割单元和决定单元。文件服务器存储由程序和数据组成的系统数据。分割单元可操作地连接到文件服务器，将系统数据划分为功能单元，并且准备功能处理器，每个功能处理器通过收集功能单元而构成。决定单元可操作地连接到文件服务器，并且根据在多个处理器中的每个处理器中彼此不同的操作数据的内容来确定要传送到多个处理器中的每一个的功能处理器。根据本发明，可以根据每个处理器中的不同功能，通过选择性地使用由系统数据功能处理器和操作数据功能处理器组成的功能处理器来实现处理器的有效IPL。

2. 发明授权

US5699504A Multiprocessor system formed of a plurality of duplex processors 失效
标题翻译：由多个双工处理器组成的多处理器系统
公开(公告)号：US5699504A
公开(公告)日：1997-12-16
申请号：US540446
申请日：1995-10-06
申请人： Kosei Mano
发明人： Kosei Mano
IPC分类号： C04B28/34 , G06F11/00 , G06F11/20 , G06F13/00 , G06F15/177 , G06F11/34
CPC分类号： G06F8/61 , G06F11/2041 , G06F11/2043 , G06F11/2046
摘要： A multiprocessor system includes duplex processors, each duplex processor having two processors, one being active and the other being a stand-by processor. Each processor includes a central processing unit (CPU) and main storage, the CPU being able to access the main storage in the other processor of the duplex processor. Each duplex processor is interconnected through communication buses to enable communication between any processors, and a particular processor can read a program file from program file storage and send it to each processor. For updating from an old program file to a new program file, each duplex processor is able to access each communication bus to identify an usable communication bus for each target processor, to set any communication bus to an active communication path for each target processor, and to transmit/receive data on the active communication path while setting another communication bus as a stand-by communication path. During operation of the active CPU using the old program file, the new program file is read to the main storage of the stand-by CPU, and the new program file of the stand-by CPU is started from the active CPU. Operation of the new program file in communicating between stand-by CPUs is confirmed by CPUs by using the stand-by communication path set by the active CPU, and setting all stand-by CPUs to the active CPU so that the program file is updated.
摘要翻译：多处理器系统包括双工处理器，每个双工处理器具有两个处理器，一个处于活动状态，另一个处于待机处理器。每个处理器包括中央处理单元（CPU）和主存储器，CPU能够访问双工处理器的另一处理器中的主存储器。每个双工处理器通过通信总线互连以实现任何处理器之间的通信，并且特定处理器可以从程序文件存储读取程序文件并将其发送到每个处理器。为了从旧的程序文件更新到新的程序文件，每个双工处理器能够访问每个通信总线以识别每个目标处理器的可用通信总线，将任何通信总线设置为每个目标处理器的主动通信路径，以及在主动通信路径上发送/接收数据，同时将另一通信总线设置为备用通信路径。在使用旧程序文件的活动CPU运行期间，将新的程序文件读取到待机CPU的主存储器，并且从活动CPU启动备用CPU的新程序文件。通过使用由活动CPU设置的待机通信路径，并将所有待机CPU设置为活动CPU，以便更新程序文件，CPU可以通过CPU确认新程序文件在待机CPU之间通信中的操作。

3. 发明授权

US6012151A Information processing apparatus and distributed processing control method 失效
标题翻译：信息处理装置和分布式处理控制方法
公开(公告)号：US6012151A
公开(公告)日：2000-01-04
申请号：US839911
申请日：1997-04-21
申请人： Kosei Mano
发明人： Kosei Mano
IPC分类号： G06F15/16 , G06F11/20 , H04Q3/545 , H04Q11/04 , G06F11/00
CPC分类号： G06F11/2033 , G06F11/2035 , H04L49/3081 , H04Q11/0478 , G06F11/2025 , H04L2012/5627 , H04L2012/563
摘要： An information processing apparatus includes at least one input and output devices each having a plurality of input and output ports, and a plurality of processors which, connected to the one or the plurality of input and output ports via a bus, process requests for processes requiring a use of the input and output ports in a distributed manner. At least one input and output device includes: an input and output port status management arrangement for maintaining an input and output port status table listing statuses of the plurality of input and output ports; a processor status management arrangement for maintaining a processor status table listing statuses of the plurality of processors; and a correspondence table management arrangement for managing correspondence between the plurality of input and output ports and pairs of active and standby processors, using a correspondence table, and each of the plurality of processors includes: a processor-specific input and output port status management controller for maintaining a processor-specific input and output port status management table listing statuses of the plurality of input and output ports to which a processor is assigned.
摘要翻译：信息处理装置包括至少一个输入和输出装置，每个输入和输出装置具有多个输入和输出端口，以及多个处理器，其通过总线连接到一个或多个输入和输出端口，以分布式方式使用输入和输出端口。至少一个输入和输出设备包括：输入和输出端口状态管理装置，用于维持输入和输出端口状态表列出多个输入和输出端口的状态; 处理器状态管理装置，用于维持列出所述多个处理器的状态的处理器状态表; 以及对应表管理装置，用于使用对应表管理多个输入和输出端口和主动和待机处理器对之间的对应关系，并且所述多个处理器中的每一个包括：处理器专用输入和输出端口状态管理控制器用于维护处理器特定的输入和输出端口状态管理表列出处理器被分配到的多个输入和输出端口的状态。

4. 发明授权

US5995983A Information processing apparatus and data processing method for information processing apparatus 失效
标题翻译：信息处理装置及信息处理装置的数据处理方法
公开(公告)号：US5995983A
公开(公告)日：1999-11-30
申请号：US698960
申请日：1996-08-16
申请人： Kosei Mano
发明人： Kosei Mano
IPC分类号： G06F12/16 , G06F11/14 , G06F11/16 , G06F17/30
CPC分类号： G06F11/1451 , Y10S707/99938 , Y10S707/99955
摘要： The invention provides an information processing apparatus and a data processing method for the information processing apparatus wherein software processing is performed using a program and/or data and which are improved in that the reliability of data can be raised flexibly in accordance with a degree of reliability required for the data even after operation of a system is started without using a specific backup hardware construction. The information processing apparatus is of the type wherein software processing is performed using data stored in a storage apparatus and includes a first storage apparatus for storing original data, a second storage apparatus for storing preliminary data which can back up the original data and can be used similarly to the original data in the software processing, and a data duplicating registration section for storing a relation between the original data and the preliminary data into a storage table.
摘要翻译：本发明提供了一种用于信息处理装置的信息处理装置和数据处理方法，其中使用程序和/或数据执行软件处理，并且其被改进为可以根据可靠程度灵活地提高数据的可靠性即使在不使用特定的备份硬件结构的情况下启动系统操作之后，数据也是必需的。信息处理装置是其中使用存储在存储装置中的数据执行软件处理的类型，并且包括用于存储原始数据的第一存储装置，用于存储可以备份原始数据并可以使用的初步数据的第二存储装置类似于软件处理中的原始数据，以及用于将原始数据和初步数据之间的关系存储到存储表中的数据复制注册部分。

5. 发明授权

US5867705A Device control apparatus and method of controlling parallel execution of device-control instructions to devices of a system 失效
标题翻译：设备控制装置和控制装置控制指令并行执行到系统装置的方法
公开(公告)号：US5867705A
公开(公告)日：1999-02-02
申请号：US723023
申请日：1996-09-30
申请人： Kosei Mano
发明人： Kosei Mano
IPC分类号： H04Q3/545 , G06F9/38 , G06F9/50 , G06F15/16 , G06F9/00
CPC分类号： G06F9/5011 , G06F9/3851
摘要： A device control apparatus includes a request accepting unit which accepts a device control request, the device control request containing an instruction code indicating a specified instruction and a device identifier indicating a specified device. A competition control unit includes a set of competition definition tables for respective devices and respective device-control instructions, reads out one of the competition definition tables by the device control request, and recognizes competition states between in-process instructions to competition devices and the specified instruction to the specified device by using the read-out competition definition table. A parallel execution control unit performs execution of one or a plurality of the specified instruction and the in-process instructions in accordance with the competition states when a sum of a first weight for the specified instruction and a second weight for the in-process instructions is less than a maximum weight.
摘要翻译：一种设备控制装置，包括接收设备控制请求的请求接收单元，包含指示指定指令的指令代码的设备控制请求以及指示设备的设备标识符。比赛控制单元包括一组针对各个装置的竞赛定义表和各自的装置控制指令，通过装置控制请求读出比赛定义表之一，并且识别竞争装置的进程内指令与规定的比赛状态通过使用读出的比赛定义表指定给指定的设备。并行执行控制单元根据竞争状态执行一个或多个指定指令和进程内指令，当指定指令的第一加权和进程内指令的第二加权之和为小于最大重量。

6. 发明授权

US06259768B1 Method of, and apparatus for, carrying out loopback test in exchange 失效
标题翻译：用于进行环回测试的方法和装置
公开(公告)号：US06259768B1
公开(公告)日：2001-07-10
申请号：US09243385
申请日：1999-02-01
申请人： Tomomi Kato , Masatoshi Takita , Kazuei Ohnishi , Takamitsu Saito , Kosei Mano
发明人： Tomomi Kato , Masatoshi Takita , Kazuei Ohnishi , Takamitsu Saito , Kosei Mano
IPC分类号： H04M124
CPC分类号： H04M3/323 , H04M3/08 , H04M3/244 , H04M2203/055
摘要： A method employs simple procedures to speedily carry out loopback tests on devices that form a channel system of an exchange. The method is capable of quickly locating a fault in the exchange and allowing speedy maintenance work of the exchange. Also provided is an apparatus for achieving the method. The apparatus has a path setter (1-4), a loopback controller (1-3), and a tester (1-1), to test the devices of the channel system (1-2) of the exchange. The devices to be tested are arranged in replaceable units (1-21, 1-22). The path setter (1-4) simultaneously sets paths to sequentially connect the devices to be tested. The loopback controller (1-3) activates and releases loopback parts arranged in the devices to be tested. The tester (1-1) sends a test signal to the devices through the paths, receives the test signal looped back by the loopback parts, analyzes the received signal, and determines whether or not the devices are sound.
摘要翻译：一种方法采用简单的程序来快速地对形成交换机的信道系统的设备进行环回测试。该方法能够快速定位交换中的故障并允许交换机的快速维护工作。还提供了一种用于实现该方法的装置。该设备具有路径设置器（1-4），环回控制器（1-3）和测试器（1-1）），用于测试交换机的信道系统（1-2）的设备。要测试的设备被布置在可更换单元（1-21,1-22）中。路径设置器（1-4）同时设置路径以顺序连接要测试的设备。环回控制器（1-3）激活并释放布置在要测试的设备中的环回部件。测试仪（1-1）通过路径向设备发送测试信号，接收环回部分环回的测试信号，分析接收到的信号，并确定设备是否正常。

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