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    • 1. 发明授权
    • Resistor-capacitor oscillation circuit capable of adjusting oscillation frequency and method of the same
    • 电阻电容振荡电路能够调节振荡频率及其方法
    • US07612624B2
    • 2009-11-03
    • US11928720
    • 2007-10-30
    • Joon Hyung LimTah Joon ParkKwang Mook LeeKoon Shik Cho
    • Joon Hyung LimTah Joon ParkKwang Mook LeeKoon Shik Cho
    • H03K3/02
    • H03K3/011H03L7/06
    • An RC oscillation circuit and method capable of adjusting an oscillation frequency includes: an RC oscillator including a variable resistor and a variable capacitor, the RC oscillator generating an RC oscillating signal having a frequency determined by a resistance of the variable resistor and a capacitance of the variable capacitor; a counter counting a clock number of a reference oscillating signal corresponding to one period of the RC oscillating signal to generate a first count value, the reference oscillating signal having a preset frequency; and a frequency controller controlling a frequency of the RC oscillating signal by determining the resistance of the variable resistor and the capacitance of the variable capacitor such that a difference between the first count value and a preset second count value is smaller than a preset first critical value.
    • 一种能够调节振荡频率的RC振荡电路和方法包括:RC振荡器,包括可变电阻器和可变电容器,RC振荡器产生具有由可变电阻器的电阻确定的频率的RC振荡信号和 可变电容器 计数对应于RC振荡信号的一个周期的参考振荡信号的时钟数,以产生第一计数值,所述参考振荡信号具有预置频率; 以及频率控制器,通过确定可变电阻器的电阻和可变电容器的电容来控制RC振荡信号的频率,使得第一计数值和预设的第二计数值之间的差小于预设的第一临界值 。
    • 3. 发明申请
    • SLEEP CURRENT ADJUSTING CIRCUIT OF SYSTEM ON CHIP
    • 休眠电流调节系统芯片电路
    • US20080278139A1
    • 2008-11-13
    • US12105966
    • 2008-04-18
    • Yong Il KwonMyeung Su KimJoon Hyung LimKoon Shik ChoTah Joon Park
    • Yong Il KwonMyeung Su KimJoon Hyung LimKoon Shik ChoTah Joon Park
    • H02M3/156
    • G11C5/14G11C5/148
    • There is provided a sleep current adjusting circuit of a system on chip including: a regulator supplying a turn-on voltage and a normal current when a mode selection signal is a normal mode signal, and a turn-off voltage when the mode selection signal is a sleep mode signal; a switching device turned on by the turn-on voltage of the regulator to supply the normal current from the regulator to a main circuit part and a sleep operation circuit part, respectively, and turned off by the turn-off voltage of the regulator to block the normal current from being supplied to the main circuit part and supply the sleep current to the sleep operation circuit part; and a current limit device limiting an operating current flowing in response to the operating voltage and supplying the sleep current to the sleep operation circuit part.
    • 提供了一种片上系统的睡眠电流调节电路,包括:当模式选择信号是正常模式信号时,提供接通电压和正常电流的调节器,以及当模式选择信号为 睡眠模式信号; 开关装置由调节器的导通电压导通,以分别将调节器的正常电流提供给主电路部分和睡眠操作电路部分,并通过调节器的截止电压将其截止以阻止 正常电流被提供给主电路部分并将睡眠电流提供给睡眠操作电路部分; 以及电流限制装置,其限制响应于所述工作电压流动的工作电流并将睡眠电流提供给所述睡眠操作电路部分。
    • 4. 发明申请
    • DUAL MODE WPAN TRANSCEIVER
    • 双模WPAN收发器
    • US20080137570A1
    • 2008-06-12
    • US11951040
    • 2007-12-05
    • Sang Hyun MINTah Joon ParkKoon Shik ChoJae Hyung Lee
    • Sang Hyun MINTah Joon ParkKoon Shik ChoJae Hyung Lee
    • H04B7/00H04L27/00
    • H04L27/3872H04B1/005H04B1/707H04B1/7163H04B1/71635H04B1/71637H04B2201/70705
    • There is provided a dual mode WPAN transceiver including a dual mode WPAN transmitter and a dual mode WPAN receiver. In the dual mode WPAN transceiver, the dual mode WPAN transmitter includes a low-speed spreading transmission block spreading low bit-rate data corresponding to a low data rate in low data rate mode, and a high-speed encoding transmission block encoding high bit-rate data corresponding to a high data rate in high data rate mode, and the dual mode WPAN receiver includes an A/D block converting analog I and Q signals into digital I and Q signals, a differential block obtaining a phase difference between the digital I and Q signals from the A/D unit and complex signals adjacent thereto to offset phase errors of the digital I and Q signals, a low-speed despreading reception unit despreading the digital I and Q signals differentiated by the differential block to detect low bit-rate data in low data rate mode, and a high-speed decoding reception unit decoding the digital I and Q signals differentiated by the differential block to detect high bit-rate data.
    • 提供了一种双模WPAN收发器,包括双模WPAN发送器和双模WPAN接收器。 在双模WPAN收发器中,双模WPAN发送器包括一个低速扩展传输块,它以低数据速率模式扩展对应于低数据速率的低比特率数据,以及一个高位编码传输块, 速率数据对应于高数据速率模式下的高数据速率,双模WPAN接收机包括将模拟I和Q信号转换成数字I和Q信号的A / D块,差分块获得数字I 和来自A / D单元的Q信号和与其相邻的复信号以消除数字I和Q信号的相位误差;低速解扩接收单元解扩由差分块区分的数字I和Q信号,以检测低位 - 低数据速率模式的速率数据,以及对由差分块区分的数字I和Q信号进行解码以检测高比特率数据的高速解码接收单元。
    • 5. 发明申请
    • SYNCHRONIZATION DEVICE AND METHOD FOR WIRELESS COMMUNICATION PACKETS
    • 用于无线通信分组的同步设备和方法
    • US20080101516A1
    • 2008-05-01
    • US11925121
    • 2007-10-26
    • Koon Shik ChoSeung Han KoJae Hyung LeeKwang Mook LeeSang Hyun MinSang Ho LeeU Sang Lee
    • Koon Shik ChoSeung Han KoJae Hyung LeeKwang Mook LeeSang Hyun MinSang Ho LeeU Sang Lee
    • H04L7/02
    • H04L7/08
    • Provided is a synchronization device for wireless communication packets, the synchronization device including an A/D (analog/digital) converter that converts an analog input signal applied from outside into a digital signal; a correlation calculating section that is connected to the A/D converter and correlates the converted input signal with a preset reference code so as to calculate a correlation value; a threshold setting section that is connected to the correlation calculating section and sets a threshold value of the correlation value; a maximum correlation detecting section that is connected to the correlation calculating section and the threshold setting section, compares the correlation value with the threshold value, detects the position of the maximum correlation value within each symbol of the input signal when the correlation value is larger than the threshold value, and judges whether a difference in position between the maximum correlation values of consecutive symbols is equal to the period of one symbol or not; a preamble detecting section that is connected to the correlation calculating section and the maximum correlation detecting section and outputs a preamble detection signal when the difference is equal to the period of one symbol; and a data detecting section that receives data of the input signal when the preamble detection signal is applied.
    • 提供了一种用于无线通信分组的同步装置,该同步装置包括将从外部施加的模拟输入信号转换为数字信号的A / D(模拟/数字)转换器; 相关计算部分,连接到A / D转换器,并将转换的输入信号与预置的参考码相关联,以便计算相关值; 阈值设定部,与相关计算部连接并设定相关值的阈值; 连接到相关计算部分和阈值设定部分的最大相关检测部分将相关值与阈值进行比较,当相关值大于该值时,检测输入信号的每个符号内的最大相关值的位置 阈值,并且判断连续符号的最大相关值之间的位置差是否等于一个符号的周期; 前同步码检测部,其连接到所述相关计算部和所述最大相关检测部,并且当所述差等于一个符号的周期时,输出前同步码检测信号; 以及数据检测部分,当应用前导码检测信号时,接收输入信号的数据。
    • 9. 发明申请
    • MULTI-VOLTAGE REGULATOR
    • 多电平稳压器
    • US20120169305A1
    • 2012-07-05
    • US13329942
    • 2011-12-19
    • Yong Il KWONTah Joon ParkKoon Shik Cho
    • Yong Il KWONTah Joon ParkKoon Shik Cho
    • G05F1/10
    • G05F3/24
    • Disclosed herein is a multi-voltage regulator. The multi-voltage regulator includes an error amplifier amplifying a difference voltage between a predetermined reference voltage and a received feedback voltage; a first voltage adjusting part connected to an output terminal of the error amplifier, the first voltage adjusting part regulating a level of a voltage at a power input terminal to output the regulated voltage to a first output terminal; a second voltage adjusting part connected to the output terminal of the error amplifier, the second voltage adjusting part regulating the level of the voltage at the power input terminal to output the regulated voltage to a second output terminal; and a voltage detector detecting a voltage according to a voltage at the first output terminal and a voltage at the second output terminal to supply the detected voltage as the feedback voltage.
    • 这里公开了一种多电压调节器。 多电压调节器包括误差放大器,放大预定参考电压和接收反馈电压之间的差分电压; 第一电压调节部分连接到误差放大器的输出端子,第一电压调节部分调节电源输入端子处的电压电平,以将调节电压输出到第一输出端子; 第二电压调节部分连接到误差放大器的输出端子,第二电压调节部分调节电源输入端子处的电压电平以将调节电压输出到第二输出端子; 以及电压检测器,根据第一输出端子处的电压和第二输出端子处的电压来检测电压,以将检测到的电压提供为反馈电压。
    • 10. 发明申请
    • APPARATUS AND SYSTEM FOR VIEWING 3D IMAGE
    • 用于查看3D图像的装置和系统
    • US20110254756A1
    • 2011-10-20
    • US12827026
    • 2010-06-30
    • Jae Hyung LEEKoon Shik CHO
    • Jae Hyung LEEKoon Shik CHO
    • G09G5/00
    • G09G3/20G09G3/003G09G2330/021H04N13/341H04N13/398H04N2213/008
    • An apparatus and a system for viewing a 3D image including a synchronization signal receiver for receiving 3D image synchronization signal; a 3D control signal generator for generating left-eye glass control signal and a right-eye glass control signal in accordance with the synchronization signal received; a left-eye glass that opens or intercepts light transmitted to the left-eye glass; a right-eye glass that opens or intercepts light transmitted to the right-eye glass; a central processor that controls operation of the 3D control signal generator and transmits the synchronization signal to the 3D control signal generator; and a power controller that connects or intercepts power supplied to the synchronization signal receiver and the central processor. The power consumption of the apparatus is minimized by supplying power to the synchronization signal receiver and the central processor at a time when the synchronization signal is received and power is intercepted during the rest period.
    • 一种用于观看包括用于接收3D图像同步信号的同步信号接收器的3D图像的装置和系统; 用于根据所接收的同步信号产生左眼玻璃控制信号和右眼玻璃控制信号的3D控制信号发生器; 打开或拦截透射到左眼玻璃的光的左眼玻璃; 打开或拦截透射到右眼玻璃的光的右眼玻璃; 控制3D控制信号发生器的操作并将同步信号发送到3D控制信号发生器的中央处理器; 以及功率控制器,其连接或截取提供给同步信号接收器和中央处理器的功率。 在同步信号被接收并且在休息期间被截取电力的时刻,通过向同步信号接收机和中央处理器供电来使设备的功耗最小化。