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1. 发明授权

US06978431B2 Automatic placement and routing apparatus automatically inserting a capacitive cell 失效
标题翻译：自动放置和布线设备自动插入电容单元
公开(公告)号：US06978431B2
公开(公告)日：2005-12-20
申请号：US10374059
申请日：2003-02-27
申请人： Koji Hirakimoto , Yoshio Inoue
发明人： Koji Hirakimoto , Yoshio Inoue
IPC分类号： G06F17/50 , H01L21/82 , G06F9/45
CPC分类号： G06F17/5036 , G06F17/5068
摘要： A redundancy detection unit refers to layout data stored in a data storage unit and reflecting completed automatic placement and routing to detect a redundant region in a region having a cell arranged therein. An automatic insertion unit inserts in the detected redundant region a capacitive cell having a capacitive component and free of logic. As such a voltage drop can be reduced in a region scarce of LSI wiring resources. Furthermore, increased wiring capacitance can be provided without increased LSI chip area.
摘要翻译：冗余检测单元是指存储在数据存储单元中的布局数据，并且反映完成的自动放置和路由以检测其中布置有单元的区域中的冗余区域。自动插入单元在检测到的冗余区域中插入具有电容分量并且没有逻辑的电容单元。由于在LSI布线资源稀少的区域中可以降低电压降。此外，可以提供增加的布线电容，而不增加LSI芯片面积。

2. 发明授权

US06711726B2 Automatic cell placement and routing apparatus and automatic cell placement and routing method used for the apparatus 失效
标题翻译：自动电池放置和布线设备以及用于设备的自动电池放置和布线方法
公开(公告)号：US06711726B2
公开(公告)日：2004-03-23
申请号：US09827932
申请日：2001-04-09
申请人： Koji Hirakimoto , Ken Saito , Tatsuya Umeda
发明人： Koji Hirakimoto , Ken Saito , Tatsuya Umeda
IPC分类号： G06F1750
CPC分类号： G06F17/5068
摘要： A buffer cell and an inverter cell are embedded in advance in an internal open space of each of mega-cells and IO cells composing a semiconductor integrated circuit. Thereafter, in cases where it is expected that a cross-talk noise is generated in a signal transmitting through a particular wire of the semiconductor integrated circuit, one mega-cell or one IO cell, which is placed in a position nearest to a generation position of the cross-talk noise, is selected from the mega-cells and the IO cells, and the buffer cell or the inverter cell embedded in the selected mega-cell or the selected IO cell is inserted into the particular wire. Therefore, because the capacitance between the particular wire and each wire adjacent to the particular wire is reduced, the cross-talk noise can be reduced.
摘要翻译：预先将缓冲单元和反相器单元嵌入构成半导体集成电路的各单元和IO单元的内部开放空间中。此后，在期望在通过半导体集成电路的特定导线发送的信号中产生串扰噪声的情况下，放置在最靠近发电位置的位置的一个兆电池或一个IO电池的串扰噪声是从巨型单元和IO单元中选出的，并且嵌入所选择的单元格或所选择的IO单元中的缓冲单元或反相器单元插入到特定的导线中。因此，由于特定导线和与特定导线相邻的每根线之间的电容减小，所以可以降低串扰噪声。

3. 发明授权

US07017134B2 Automatic floor-planning method capable of shortening floor-plan processing time 有权
标题翻译：自动楼层规划方法能够缩短平面图处理时间
公开(公告)号：US07017134B2
公开(公告)日：2006-03-21
申请号：US10836324
申请日：2004-05-03
申请人： Ken Saito , Yoshio Inoue , Koji Hirakimoto
发明人： Ken Saito , Yoshio Inoue , Koji Hirakimoto
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , H01L27/0203
摘要： An automatic floor-planning method includes extracting a register and a logic operation cell in a semiconductor integrated-circuit unit, extracting a first register set and a second register set that are assumed to input and receive a signal to and from the logic operation cell directly or via other logic operation cell, respectively, creating a set of the logic operation cells as a cluster cell, determining a layout of the cluster cell and the register, selecting a logic level block for which a floor plan is performed, and determining an arrangement and wiring area such that the arrangement and wiring area of the logic level block includes as many cells as possible that belong to the logic level block.
摘要翻译：自动楼层规划方法包括提取半导体集成电路单元中的寄存器和逻辑运算单元，提取假设为直接从逻辑运算单元输入和接收信号的第一寄存器组和第二寄存器组或经由其他逻辑运算单元，创建一组逻辑运算单元作为集群单元，确定集群单元和寄存器的布局，选择执行平面图的逻辑电平块，以及确定布置和布线区域，使得逻辑电平块的布置和布线区域包括属于逻辑电平块的尽可能多的单元。

4. 发明授权

US06938232B2 Floorplanning apparatus deciding floor plan using logic seeds associated with hierarchical blocks 有权
标题翻译：布置规划设备使用与分级块相关联的逻辑种子来确定平面图
公开(公告)号：US06938232B2
公开(公告)日：2005-08-30
申请号：US10320635
申请日：2002-12-17
申请人： Ken Saito , Yoshio Inoue , Kazuhiro Takahashi , Koji Hirakimoto
发明人： Ken Saito , Yoshio Inoue , Kazuhiro Takahashi , Koji Hirakimoto
IPC分类号： G06F17/50 , H01L21/82
CPC分类号： G06F17/5072
摘要： A floorplanning apparatus includes a seed position decision section for deciding a placement position of a logic seed of each hierarchical block; a cell placement section for placing cells belonging to the hierarchical block around the placement position of each logic seed; and a placement region decision section for deciding placement and routing regions of each hierarchical block considering cell placement results produced by the cell placement section.
摘要翻译：布局规划设备包括种子位置决定部分，用于确定每个分级块的逻辑种子的放置位置; 单元放置部，用于将属于分层块的单元放置在每个逻辑种子的放置位置周围; 以及放置区域判定部，其考虑由所述单元放置部生成的单元布置结果，决定各分层块的布局和布线区域。

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