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1. 发明专利

JP2004084424A Sand removing device for snow melting device for road and the like 有权
标题翻译：用于道路和雪橇的修磨装置的桑拿去除装置
公开(公告)号：JP2004084424A
公开(公告)日：2004-03-18
申请号：JP2002287484
申请日：2002-08-22
申请人： Koji Eguchi , 江口幸司
发明人： EGUCHI KOJI
IPC分类号： E01H3/04
摘要： PROBLEM TO BE SOLVED: To provide a sand removing device that prevents traffic disaster by drastically increasing stability of a snow melting effect and reduces maintenance of a snow melting device.
SOLUTION: The sand removing device has a first separation tank I for receiving discharge water from a submersible pump, second separation tanks II for receiving two respective flows of guided water, and a water supply line 6 for recombining the guided water flows from the second separation tanks to feed the confluence to a snow melting pipe. A sand discharge pipe 7 with a solenoid valve 8 is arranged in a lower portion of each separation tank, and a control circuit for releasing the solenoid valve either at a stop of the submersible pump or a given time before the stop according to a signal from a snowfall sensor is added to a control panel 13 of the submersible pump, so that sand in a snow melting device for a road and the like is removed. In a region with a small sand lift, the operation/stop cycle of the submersible pump is counted, and the solenoid valve 8 is opened in every plural cycles to eliminate unnecessary operation of sand discharge.
COPYRIGHT: (C)2004,JPO
摘要翻译：要解决的问题：提供一种通过大幅提高雪融化效果的稳定性来防止交通事故的除砂装置，并减少雪融化装置的维护。解决方案：除砂装置具有用于从潜水泵接收排出水的第一分离罐I，用于接收两个相应的导向水流的第二分离罐II和用于将引导水流从第二分离罐将汇合物供给融雪管。具有电磁阀8的排沙管7设置在每个分离罐的下部，以及控制电路，用于在潜水泵的停止处或在停止之前的给定时间根据来自将降雪传感器添加到潜水泵的控制面板13中，从而去除用于道路等的雪融化装置中的沙子。在具有小砂提升的区域中，计数潜水泵的操作/停止循环，并且电磁阀8每隔几个循环打开以消除不必要的排砂操作。版权所有（C）2004，JPO

2. 发明专利

JP2004033229A Chemical spray attachment 有权
公开(公告)号：JP2004033229A
公开(公告)日：2004-02-05
申请号：JP2003368917
申请日：2003-10-29
申请人： Abe Hideyuki , Koji Eguchi , Jinko Takase , 江口浩司 , 阿部秀之 , 高瀬仁孝
发明人： EGUCHI KOJI , TAKASE JINKO
IPC分类号： A01M7/00 , B05B17/00
摘要： PROBLEM TO BE SOLVED: To provide a chemical spray attachment applicable to spraying chemicals over a steeply inclined slope and the like by being attached to a vehicle for slope work, excellent in work efficiency and safety and capable of spraying at a low cost.
SOLUTION: The chemical spray attachment is attached to an existing vehicle for slope work and applied to receiving chemicals from an outer tank and performing chemical spray and comprises a swingable arm supporting a chemical hose transferring the chemicals supplied from the outer tank, an arm-supporting element set at the horizontal center of the vehicle for slope work and having a U-shaped nipping part supporting the swingable arm, a chemical spray nozzle attached to the tip of the chemical hose and spraying the chemicals and a nozzle-fixing element, wherein one end of the swinging arm is nipped by a U-shaped support from the upper and lower sides and is supported rotatably around the end.
COPYRIGHT: (C)2004,JPO

3. 发明授权

US07298020B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07298020B2
公开(公告)日：2007-11-20
申请号：US10797081
申请日：2004-03-11
申请人： Syuji Asano , Yoshiaki Nakayama , Koji Eguchi
发明人： Syuji Asano , Yoshiaki Nakayama , Koji Eguchi
IPC分类号： H01L29/00
CPC分类号： H01L28/24 , H01L21/8221 , H01L27/0688
摘要： A wire (12) is formed on an insulating film (10) on a semiconductor substrate (1). The wire (12) is covered by silicon nitride film (14), inorganic SOG film (20) and TEOS film (21). A thin film resistance element (30) of chromium silicon (CrSi) is formed on the upper surface of the TEOS film (21). The acute angle (taper angle) at which a line connecting the local maximum and minimum points of a step on the upper surface of the TEOS film (21) beneath the area where the thin film resistance element (30) is formed intersects to the surface of the substrate (1) is set to 10° or less.
摘要翻译：在半导体衬底（1）上的绝缘膜（10）上形成导线（12）。线（12）由氮化硅膜（14），无机SOG膜（20）和TEOS膜（21）覆盖。在TEOS膜（21）的上表面上形成有铬硅（CrSi）的薄膜电阻元件（30）。连接薄膜电阻元件（30）形成区域下方的TEOS薄膜（21）的上表面上的台阶的局部最大值和最小点的线的锐角（锥角）与表面的基板（1）设定为10°以下。

4. 发明授权

US5200807A Wiring connection structure for a semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件的接线连接结构
公开(公告)号：US5200807A
公开(公告)日：1993-04-06
申请号：US520482
申请日：1990-05-08
申请人： Koji Eguchi
发明人： Koji Eguchi
IPC分类号： H01L21/3205 , H01L21/768 , H01L23/522 , H01L23/528
CPC分类号： H01L23/5283 , H01L23/5226 , H01L2924/0002
摘要： A wiring connection structure for a semiconductor integrated circuit device interconnects a plurality of wiring layers isolated by an insulating layer, via a through hole defined in the insulating layer. The wiring connection structure comprises a semiconductor substrate, a first insulating layer, a first wiring layer, a second insulating layer and a second wiring layer. The first insulating layer is formed on a main surface of the semiconductor substrate. The first wiring layer is formed on the first insulating layer. The second insulating layer is formed on the first wiring layer. The through hole is formed in the second insulating layer so as to extend to a surface of the first wiring layer. The second wiring layer is formed on the second insulating layer and connected to the first wiring layer via the through hole. The through hole is a single through hole formed in a region where the second wiring layer overlaps with the first wiring layer. The through hole has a cross section comprising a figure formed by indenting peripheries of a single rectangular figure. This cross section has a longer perimeter than the single rectangular figure. Alternatively, the cross section comprises a figure formed by interconnecting band portions extending along the second wiring layer. A reduction is achieved in components of resistance over an entire through hole forming region. Concentration of current density on side walls of the through hole is also mitigated.
摘要翻译：用于半导体集成电路器件的布线连接结构通过绝缘层中限定的通孔将由绝缘层隔离的多个布线层互连。布线连接结构包括半导体衬底，第一绝缘层，第一布线层，第二绝缘层和第二布线层。第一绝缘层形成在半导体衬底的主表面上。第一布线层形成在第一绝缘层上。第二绝缘层形成在第一布线层上。通孔形成在第二绝缘层中，以便延伸到第一布线层的表面。第二布线层形成在第二绝缘层上，并且经由通孔与第一布线层连接。通孔是形成在第二布线层与第一布线层重叠的区域中的单个通孔。通孔具有包括通过压制单个矩形图形的外围形成的图形的横截面。该横截面具有比单个矩形图形更长的周长。或者，横截面包括通过互连沿着第二布线层延伸的带部分形成的图形。在整个通孔形成区域中的电阻分量中实现了减小。通孔侧壁电流密度的集中也得到了缓解。

5. 发明授权

US06748704B2 Factory layout 失效
标题翻译：工厂布局
公开(公告)号：US06748704B2
公开(公告)日：2004-06-15
申请号：US09784024
申请日：2001-02-16
申请人： Koji Eguchi , Shintaro Matsuda , Satoru Souda , Akiko Sakai
发明人： Koji Eguchi , Shintaro Matsuda , Satoru Souda , Akiko Sakai
IPC分类号： E04H900
CPC分类号： E04H5/02 , E04B2001/0084 , E04H1/005 , Y10S52/10
摘要： A factory layout includes a plurality of substantially triangle units provided in radial directions. The triangle units are combined so as to form a polygonal shape including a triangle shape as a whole. The empty regions with an air-conditioning facility are provided at a part of the central portion of the polygonal shape.
摘要翻译：工厂布置包括沿径向设置的多个基本三角形的单元。组合三角形单元以形成整体上包括三角形的多边形形状。具有空调设备的空区域设置在多边形形状的中心部分的一部分。

6. 发明授权

US5466638A Method of manufacturing a metal interconnect with high resistance to electromigration 失效
标题翻译：制造具有高耐电迁移性的金属互连的方法
公开(公告)号：US5466638A
公开(公告)日：1995-11-14
申请号：US292542
申请日：1994-08-16
申请人： Koji Eguchi
发明人： Koji Eguchi
IPC分类号： H01L23/52 , H01L21/3205 , H01L21/768 , H01L23/522 , H01L23/532 , H01L21/283 , H01L21/324
CPC分类号： H01L23/5226 , H01L21/76877 , H01L23/53223 , H01L2924/0002 , Y10S438/927
摘要： A semiconductor device is provided which includes a conductive layer, an insulating film formed on the surface of the conductive layer, and a conductive metal interconnection layer formed on the insulating film and electrically connected to the conductive layer through a contact hole formed in a predetermine position of the insulating film. The conductive metal interconnection and the surface of the conductive layer are directly joined together and a silicon layer including a single crystal or polycrystalline silicon having a grain size of at least about 10 .mu.m is interposed between the conductive metal interconnection layer and the insulating film. The conductive metal interconnection layer becomes a single crystal or a polycrystal having a grain size of about 10 .mu.m or above under the influence of the crystalline properties of the underlying crystal of the silicon layer. Therefore, in the conductive metal interconnection layer in the entire region including the inside portion of the contact hole, essentially no grain boundaries exist. Thus, electromigration of conductive metal ions is controlled.
摘要翻译：提供了一种半导体器件，其包括导电层，形成在导电层表面上的绝缘膜和形成在绝缘膜上的导电金属互连层，并通过形成在预定位置的接触孔电连接到导电层的绝缘膜。导电金属互连和导电层的表面直接接合在一起，并且包括具有至少约10μm的晶粒尺寸的单晶或多晶硅的硅层插入在导电金属互连层和绝缘膜之间。在硅层的下面的晶体的结晶性质的影响下，导电性金属互连层成为具有约10μm以上的晶粒尺寸的单晶或多晶体。因此，在包括接触孔的内部的整个区域的导电性金属配线层中，基本上不存在晶界。因此，控制导电金属离子的电迁移。

7. 发明授权

US5446301A Semiconductor device including semiconductor layer having impurity region and method of manufacturing the same 失效
标题翻译：包括具有杂质区域的半导体层的半导体器件及其制造方法
公开(公告)号：US5446301A
公开(公告)日：1995-08-29
申请号：US274517
申请日：1994-07-13
申请人： Koji Eguchi , Natsuo Ajika , Kazuyuki Sugahara
发明人： Koji Eguchi , Natsuo Ajika , Kazuyuki Sugahara
IPC分类号： H01L21/20 , H01L21/336 , H01L21/768 , H01L21/84 , H01L27/06 , H01L27/12 , H01L29/49 , H01L29/78 , H01L29/786 , H01L27/01 , H01L29/06
CPC分类号： H01L29/66772 , H01L27/0688 , H01L27/1203 , H01L29/4908 , H01L29/78654
摘要： A semiconductor device capable of effectively preventing a dielectric breakdown of a gate oxide film without adversely affecting the characteristics of a transistor and a process of manufacturing the same are disclosed. The semiconductor device comprises a SOI film 2 whose upper angular parts are rounded off by sputter etching and a gate oxide film 3 formed on SOI film 2 with an almost uniform thickness. Therefore, electric field concentration in the upper angular parts of SOI film 2 is reduced. Furthermore, the control characteristics of the transistor are enhanced by the uniform gate oxide film 3. As a result, a dielectric breakdown of the gate oxide film is effectively prevented without adversely affecting the characteristics of the transistor. Sputter etching enabling processing at a low temperature is used, so that the upper angular parts of SOI film 2 are rounded off without adversely affecting a semiconductor element formed in the lower layer.
摘要翻译：公开了能够有效地防止栅极氧化膜的介电击穿而不会不利地影响晶体管的特性的半导体器件及其制造方法。该半导体器件包括通过溅射蚀刻使上角部分被倒圆的SOI膜2和形成在具有几乎均匀厚度的SOI膜2上的栅极氧化膜3。因此，SOI膜2的上角部的电场浓度降低。此外，通过均匀的栅极氧化膜3增强晶体管的控制特性。结果，有效地防止了栅极氧化膜的电介质击穿，而不会不利地影响晶体管的特性。使用能够在低温下进行的溅射蚀刻，使得SOI膜2的上角部分被倒圆而不会对形成在下层中的半导体元件产生不利影响。

8. 发明授权

US5444186A Multilayer conductive wire for semiconductor device and manufacturing method thereof 失效
标题翻译：用于半导体器件的多层导线及其制造方法
公开(公告)号：US5444186A
公开(公告)日：1995-08-22
申请号：US933633
申请日：1992-08-24
申请人： Koji Eguchi
发明人： Koji Eguchi
IPC分类号： H01L21/3205 , H01L21/768 , H01L23/52 , H01L23/522 , H01L23/528 , H01L23/532 , H01L29/41 , H05K1/00
CPC分类号： H01L21/7684 , H01L23/5226 , H01L23/5283 , H01L23/53223 , H01L2924/0002
摘要： A multilayer conductive wire is formed of a plurality of conductive layers stacked upon each other, and has a slit shaped groove extending in the direction intersecting the direction of stress in at least one conductive layer. With the groove mating with a protrusion in another conductive layer or a protrusion in an insulating film layer, a sliding phenomenon between the layers due to the stress can be restrained, so that a multilayer conductive wire free from destruction due to the sliding phenomenon caused by the stress and without losing conductivity can be provided.
摘要翻译：多层导线由彼此堆叠的多个导电层形成，并且具有沿与至少一个导电层中的应力方向相交的方向延伸的狭缝形槽。通过与另一导电层中的突起或绝缘膜层中的突起配合的槽，可以抑制由于应力而导致的层之间的滑动现象，使得由于由于滑动现象而导致的多层导电线可以提供应力并且不损失导电性。

9. 发明授权

US5381029A Semiconductor device including semiconductor layer having impurity region and method of manufacturing the same 失效
公开(公告)号：US5381029A
公开(公告)日：1995-01-10
申请号：US838993
申请日：1992-02-21
申请人： Koji Eguchi , Natsuo Ajika , Kazuyuki Sugahara
发明人： Koji Eguchi , Natsuo Ajika , Kazuyuki Sugahara
IPC分类号： H01L21/20 , H01L21/336 , H01L21/768 , H01L21/84 , H01L27/06 , H01L27/12 , H01L29/49 , H01L29/78 , H01L29/786 , H01L27/01 , H01L29/06
CPC分类号： H01L29/66772 , H01L27/0688 , H01L27/1203 , H01L29/4908 , H01L29/78654
摘要： A semiconductor device capable of effectively preventing a dielectric breakdown of a gate oxide film without adversely affecting the characteristics of a transistor and a process of manufacturing the same are disclosed. The semiconductor device comprises a SOI film 2 whose upper angular parts are rounded off by sputter etching and a gate oxide film 3 formed on SOI film 2 with an almost uniform thickness. Therefore, electric field concentration in the upper angular parts of SOI film 2 is reduced. Furthermore, the control characteristics of the transistor are enhanced by the uniform gate oxide film 3. As a result, a dielectric breakdown of the gate oxide film is effectively prevented without adversely affecting the characteristics of the transistor. Sputter etching enabling processing at a low temperature is used, so that the upper angular parts of SOI film 2 are rounded off without adversely affecting a semiconductor element formed in the lower layer.

10. 发明授权

US5373192A Electromigration resistance metal interconnect 失效
标题翻译：电镀金属互连
公开(公告)号：US5373192A
公开(公告)日：1994-12-13
申请号：US936060
申请日：1992-08-28
申请人： Koji Eguchi
发明人： Koji Eguchi
IPC分类号： H01L23/52 , H01L21/3205 , H01L21/768 , H01L23/522 , H01L23/532 , H01L23/48 , H01L29/44 , H01L29/52 , H01L29/60
CPC分类号： H01L23/5226 , H01L21/76877 , H01L23/53223 , H01L2924/0002 , Y10S438/927
摘要： A semiconductor device is provided which includes a conductive layer, an insulating film formed on the surface of the conductive layer, and a conductive metal interconnection layer formed on the insulating film and electrically connected to the conductive layer through a contact hole formed in a predetermined position of the insulating film. The conductive metal interconnection and the surface of the conductive layer are directly joined together and a silicon layer including a single crystal or polycrystalline silicon having a grain size of at least about 10 .mu.m is interposed between the conductive metal interconnection layer and the insulating film. The conductive metal interconnection layer becomes a single crystal or a polycrystal having a grain size of about 10 .mu.m or above under the influence of the crystalline properties of the underlying crystal of the silicon layer. Therefore, in the conductive metal interconnection layer in the entire region including the inside portion of the contact hole, essentially no grain boundaries exist. Thus, electromigration of conductive metal ions is controlled.
摘要翻译：提供了一种半导体器件，其包括导电层，形成在导电层的表面上的绝缘膜，以及形成在绝缘膜上并通过形成在预定位置的接触孔电连接到导电层的导电金属互连层的绝缘膜。导电金属互连和导电层的表面直接接合在一起，并且包括具有至少约10μm的晶粒尺寸的单晶或多晶硅的硅层插入在导电金属互连层和绝缘膜之间。在硅层的下面的晶体的结晶性质的影响下，导电性金属互连层成为具有约10μm以上的晶粒尺寸的单晶或多晶体。因此，在包括接触孔的内部的整个区域的导电性金属配线层中，基本上不存在晶界。因此，控制导电金属离子的电迁移。

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