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1. 发明授权

US07227351B2 Apparatus and method for performing parallel test on integrated circuit devices 有权
标题翻译：在集成电路设备上执行并行测试的装置和方法
公开(公告)号：US07227351B2
公开(公告)日：2007-06-05
申请号：US10856461
申请日：2004-05-27
申请人： Woo-Il Kim , Hyun-Seop Shim , Hyoung-Young Lee , Young-Ki Kwak , Jeong-Ho Bang , Ki-Bong Ju
发明人： Woo-Il Kim , Hyun-Seop Shim , Hyoung-Young Lee , Young-Ki Kwak , Jeong-Ho Bang , Ki-Bong Ju
IPC分类号： G01R31/28
CPC分类号： G01R31/31905 , G11C2029/2602
摘要： Embodiments of the invention connect a plurality of devices under test (DUTS) in a parallel manner and a high test current is selectively applied to each DUT. The apparatus to test a plurality of DUTs includes a plurality of power sources providing the test current to a plurality of DUTs; and switching devices connected to the respective DUTs and power sources and selectively providing the test current. In addition, the apparatus has at least one control unit to control the switching devices. Furthermore, a group of DUTs from the plurality of DUTs is connected between two of the plurality of power sources in a parallel manner, and the test current is selectively provided to one DUT from the group of DUTs according to the operation of the switching devices.
摘要翻译：本发明的实施例以并行方式连接多个待测器件（DUTS），并且将高测试电流选择性地施加到每个DUT。测试多个DUT的装置包括向多个DUT提供测试电流的多个电源; 以及连接到各个DUT和电源的开关装置，并选择性地提供测试电流。此外，该装置具有至少一个控制单元来控制开关装置。此外，来自多个DUT的一组DUT以并行方式连接在多个电源中的两个之间，并且根据开关装置的操作，从DUT组中选择性地向一个DUT提供测试电流。

2. 发明授权

US06943577B2 Multichip package test 失效
标题翻译： Multichip包测试
公开(公告)号：US06943577B2
公开(公告)日：2005-09-13
申请号：US10677743
申请日：2003-10-01
申请人： Young-Gu Shin , Kyoung-Il Heo , Hyoung-Young Lee , Hyuk Kwon , Ki-Bong Ju , Jeong-Ho Bang , Hyun-Seop Shim
发明人： Young-Gu Shin , Kyoung-Il Heo , Hyoung-Young Lee , Hyuk Kwon , Ki-Bong Ju , Jeong-Ho Bang , Hyun-Seop Shim
IPC分类号： G01R31/28 , G01R31/26 , G01R31/3185
CPC分类号： G01R31/318505 , G01R31/318513
摘要： A test apparatus for testing a multi-chip package comprising a multiplicity of semiconductor chips, which includes a test driver having one drive channel and at least one input/output channel. A test board is mounted with the multi-chip package. Drive pins of the semiconductor chips are parallel connected to the drive channel, and input/output pins of the semiconductor chips are parallel connected to the input/output channel.
摘要翻译：一种用于测试包括多个半导体芯片的多芯片封装的测试装置，其包括具有一个驱动通道和至少一个输入/输出通道的测试驱动器。测试板安装有多芯片封装。半导体芯片的驱动引脚并联连接到驱动通道，并且半导体芯片的输入/输出引脚并联连接到输入/输出通道。

3. 发明授权

US06199185B1 Test method for high speed semiconductor devices using a clock modulation technique 失效
标题翻译：使用时钟调制技术的高速半导体器件的测试方法
公开(公告)号：US06199185B1
公开(公告)日：2001-03-06
申请号：US09062718
申请日：1998-04-20
申请人： Ki Bong Ju , Jae Bun Ryu , Il Sik Chi , Heui Han
发明人： Ki Bong Ju , Jae Bun Ryu , Il Sik Chi , Heui Han
IPC分类号： G01R3128
CPC分类号： G11C29/48
摘要： A test method for testing a semiconductor device includes providing a tester which generates a plurality of general clock signals and which has a minimum test cycle time greater than an operational cycle time of the semiconductor device. Then a modulated clock signal is generated from a first general clock signal and a second general clock signal so that the modulated clock signal has a minimum cycle time no greater than the operational cycle time. The next steps include supplying the modulated clock signal to the semiconductor device as a predetermined control signal, supplying test signals to the semiconductor device as specified by a functional test item, and comparing an output of the semiconductor device to a reference value.
摘要翻译：一种用于测试半导体器件的测试方法包括提供产生多个通用时钟信号并且具有大于半导体器件的操作周期时间的最小测试周期时间的测试器。然后，从第一通用时钟信号和第二通用时钟信号产生调制时钟信号，使得调制时钟信号具有不大于工作周期时间的最小周期时间。接下来的步骤包括将调制的时钟信号作为预定的控制信号提供给半导体器件，将功能测试项目规定的测试信号提供给半导体器件，并将半导体器件的输出与参考值进行比较。

4. 发明申请

US20050007140A1 Apparatus and method for performing parallel test on integrated circuit devices 有权
标题翻译：在集成电路设备上执行并行测试的装置和方法
公开(公告)号：US20050007140A1
公开(公告)日：2005-01-13
申请号：US10856461
申请日：2004-05-27
申请人： Woo-Il Kim , Hyun-Seop Shim , Hyoung-Young Lee , Young-Ki Kwak , Jeong-Ho Bang , Ki-Bong Ju
发明人： Woo-Il Kim , Hyun-Seop Shim , Hyoung-Young Lee , Young-Ki Kwak , Jeong-Ho Bang , Ki-Bong Ju
IPC分类号： G01R31/28 , G01R31/319 , G11C29/00 , G01R31/26
CPC分类号： G01R31/31905 , G11C2029/2602
摘要： Embodiments of the invention connect a plurality of devices under test (DUTS) in a parallel manner and a high test current is selectively applied to each DUT. The apparatus to test a plurality of DUTs includes a plurality of power sources providing the test current to a plurality of DUTs; and switching devices connected to the respective DUTs and power sources and selectively providing the test current. In addition, the apparatus has at least one control unit to control the switching devices. Furthermore, a group of DUTs from the plurality of DUTs is connected between two of the plurality of power sources in a parallel manner, and the test current is selectively provided to one DUT from the group of DUTs according to the operation of the switching devices.
摘要翻译：本发明的实施例以并行方式连接多个待测器件（DUTS），并且将高测试电流选择性地施加到每个DUT。测试多个DUT的装置包括向多个DUT提供测试电流的多个电源; 以及连接到各个DUT和电源的开关装置，并选择性地提供测试电流。此外，该装置具有至少一个控制单元来控制开关装置。此外，来自多个DUT的一组DUT以并行方式连接在多个电源中的两个之间，并且根据开关装置的操作，从DUT组中选择性地向一个DUT提供测试电流。

5. 发明授权

US07327154B2 Multichip package test 失效
标题翻译： Multichip包测试
公开(公告)号：US07327154B2
公开(公告)日：2008-02-05
申请号：US11191494
申请日：2005-07-27
申请人： Young-Gu Shin , Kyoung-Il Heo , Hyoung-Young Lee , Hyuk Kwon , Ki-Bong Ju , Jeong-Ho Bang , Hyun-Seop Shim
发明人： Young-Gu Shin , Kyoung-Il Heo , Hyoung-Young Lee , Hyuk Kwon , Ki-Bong Ju , Jeong-Ho Bang , Hyun-Seop Shim
IPC分类号： G01R31/28
CPC分类号： G01R31/318505 , G01R31/318513
摘要： A test apparatus for testing a multi-chip package comprising a multiplicity of semiconductor chips, which includes a test driver having one drive channel and at least one input/output channel. A test board is mounted with the multi-chip package. Drive pins of the semiconductor chips are parallel connected to the drive channel, and input/output pins of the semiconductor chips are parallel connected to the input/output channel.
摘要翻译：一种用于测试包括多个半导体芯片的多芯片封装的测试装置，其包括具有一个驱动通道和至少一个输入/输出通道的测试驱动器。测试板安装有多芯片封装。半导体芯片的驱动引脚并联连接到驱动通道，并且半导体芯片的输入/输出引脚并联连接到输入/输出通道。

6. 发明申请

US20050258858A1 Multichip package test 失效
公开(公告)号：US20050258858A1
公开(公告)日：2005-11-24
申请号：US11191494
申请日：2005-07-27
申请人： Young-Gu Shin , Kyoung-Il Heo , Hyoung-Young Lee , Hyuk Kwon , Ki-Bong Ju , Jeong-Ho Bang , Hyun-Seop Shim
发明人： Young-Gu Shin , Kyoung-Il Heo , Hyoung-Young Lee , Hyuk Kwon , Ki-Bong Ju , Jeong-Ho Bang , Hyun-Seop Shim
IPC分类号： G01R31/28 , G01R31/26 , G01R31/3185
CPC分类号： G01R31/318505 , G01R31/318513
摘要： A test apparatus for testing a multi-chip package comprising a multiplicity of semiconductor chips, which includes a test driver having one drive channel and at least one input/output channel. A test board is mounted with the multi-chip package. Drive pins of the semiconductor chips are parallel connected to the drive channel, and input/output pins of the semiconductor chips are parallel connected to the input/output channel.

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