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1. 发明申请

US20100123215A1 Capacitor Die Design for Small Form Factors 审中-公开
标题翻译：小型电容器模具设计
公开(公告)号：US20100123215A1
公开(公告)日：2010-05-20
申请号：US12620884
申请日：2009-11-18
申请人： Yuancheng Christopher Pan , Fifin Sweeney , Charlie Paynter , Kevin R. Bowles , Jason R. Gonzalez
发明人： Yuancheng Christopher Pan , Fifin Sweeney , Charlie Paynter , Kevin R. Bowles , Jason R. Gonzalez
IPC分类号： H01L23/52 , H01L21/50 , H01L23/498
CPC分类号： H01L23/49816 , H01L23/50 , H01L23/5222 , H01L23/5286 , H01L23/642 , H01L24/48 , H01L24/73 , H01L25/0652 , H01L25/0657 , H01L25/105 , H01L25/16 , H01L2224/16145 , H01L2224/16225 , H01L2224/16265 , H01L2224/32225 , H01L2224/48227 , H01L2224/73203 , H01L2224/73204 , H01L2224/73265 , H01L2225/06517 , H01L2225/06541 , H01L2225/06572 , H01L2225/1058 , H01L2924/00011 , H01L2924/00014 , H01L2924/13091 , H01L2924/14 , H01L2924/15184 , H01L2924/15311 , H01L2924/19041 , H01L2924/19104 , H01L2924/19105 , H01L2924/19106 , H01L2924/19107 , H01L2924/30107 , H01L2924/3011 , H01L2924/00 , H01L2924/00012 , H01L2224/32145 , H01L2224/48145 , H01L2224/0401 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor package has a capacitor die and a packaging substrate. The capacitor die is coupled to circuitry on a front or back side of a die coupled to the packaging substrate for providing decoupling capacitance. In one example, the capacitor die is coupled to a land side of the packaging substrate in an area depopulated of a packaging array and adjacent to the packaging array. In another example, the capacitor die may be stacked on the die and coupled through wire bonds to circuitry on the die. The capacitor die reduces impedance of the integrated circuit allowing operation at higher frequencies.
摘要翻译：半导体封装具有电容器裸片和封装衬底。电容器管芯耦合到耦合到封装衬底的管芯的前侧或后侧上的电路，用于提供去耦电容。在一个示例中，电容器裸片在包装阵列的填充区域中并且与封装阵列相邻的区域耦合到封装衬底的接地侧。在另一示例中，电容器管芯可以堆叠在管芯上并且通过引线接合耦合到管芯上的电路。电容器管芯降低了集成电路的阻抗，允许在较高频率下工作。

2. 发明授权

US07100022B1 Area and power efficient VLIW processor with improved speed 有权
标题翻译：面积和功率高效的VLIW处理器具有改进的速度
公开(公告)号：US07100022B1
公开(公告)日：2006-08-29
申请号：US10085724
申请日：2002-02-28
申请人： Moataz Mohamed , John Spence , Kevin R. Bowles , Chien-Wei Li
发明人： Moataz Mohamed , John Spence , Kevin R. Bowles , Chien-Wei Li
IPC分类号： G06F15/16 , G06F15/00
CPC分类号： G06F9/3885 , G06F9/3012 , G06F9/30141 , G06F9/3824 , G06F9/3828 , G06F9/3853
摘要： In one embodiment, move buses utilized in presently known VLIW processors are eliminated and replaced with a busing scheme which results in transfer of operands from each register file bank to any data path block while also reducing the total bus width and total power consumption associated with transport of operands from register file banks to data path blocks. According to this busing scheme, the speed of VLIW processor is also improved since the need for one clock cycle to move operands from one register file bank to another is overcome. In another embodiment, a scheduling restriction is used to eliminate the need for the presently required write back buses used by various data path blocks. In yet another embodiment, a scheduling restriction is imposed which results in a reduction of the number of ports, a reduction in the width of buses, and a reduction of power consumption.
摘要翻译：在一个实施例中，消除了在当前已知的VLIW处理器中使用的移动总线，并且将其替换为导致将操作数从每个寄存器文件组传送到任何数据路径块的通配方案，同时还减少与传输相关联的总总线宽度和总功率消耗从寄存器文件库到数据路径块的操作数。根据这种调用方案，VLIW处理器的速度也得到了提高，因为克服了从一个寄存器文件组到另一个寄存器堆栈将操作数移动到另一个时钟周期的需要。在另一个实施例中，使用调度限制来消除对各种数据路径块使用的当前所需的回写总线的需要。在另一个实施例中，施加调度限制，这导致端口数量的减少，总线宽度的减小以及功耗的降低。

3. 发明授权

US08433944B2 Clock divider system and method with incremental adjustment steps while controlling tolerance in clock duty cycle 失效
标题翻译：时钟分频器系统和方法具有增量调节步骤，同时控制时钟占空比的容限
公开(公告)号：US08433944B2
公开(公告)日：2013-04-30
申请号：US12758374
申请日：2010-04-12
申请人： Srinjoy Das , Haikun Zhu , Kevin R. Bowles , Matthew L. Severson
发明人： Srinjoy Das , Haikun Zhu , Kevin R. Bowles , Matthew L. Severson
IPC分类号： G06F1/00
CPC分类号： G06F1/08 , H03K21/10 , H03K21/38
摘要： In a particular embodiment, a single step increment calculation module is responsive to a first ramp control value and a second ramp control value. The single step increment calculation module generates a single step frequency adjustment as an output. The generated single step frequency adjustment is applied to a system clock signal having a first frequency to change the system clock signal to a second clock signal having a second frequency. The first frequency is different from the second frequency and the system clock signal has a first duty cycle that is within a tolerance range of a second duty cycle of the second clock signal.
摘要翻译：在特定实施例中，单步增量计算模块响应于第一斜坡控制值和第二斜坡控制值。单步增量计算模块生成单步频率调整作为输出。生成的单步频率调整被应用于具有第一频率的系统时钟信号，以将系统时钟信号改变为具有第二频率的第二时钟信号。第一频率与第二频率不同，并且系统时钟信号具有在第二时钟信号的第二占空比的容差范围内的第一占空比。

4. 发明申请

US20110248764A1 Clock Divider System and Method 失效
标题翻译：时钟分频系统和方法
公开(公告)号：US20110248764A1
公开(公告)日：2011-10-13
申请号：US12758374
申请日：2010-04-12
申请人： Srinjoy Das , Haikun Zhu , Kevin R. Bowles , Matthew L. Severson
发明人： Srinjoy Das , Haikun Zhu , Kevin R. Bowles , Matthew L. Severson
IPC分类号： G06F1/04
CPC分类号： G06F1/08 , H03K21/10 , H03K21/38
摘要： In a particular embodiment, a single step increment calculation module is responsive to a first ramp control value and a second ramp control value. The single step increment calculation module generates a single step frequency adjustment as an output. The generated single step frequency adjustment is applied to a system clock signal having a first frequency to change the system clock signal to a second clock signal having a second frequency. The first frequency is different from the second frequency and the system clock signal has a first duty cycle that is within a tolerance range of a second duty cycle of the second clock signal.
摘要翻译：在特定实施例中，单步增量计算模块响应于第一斜坡控制值和第二斜坡控制值。单步增量计算模块生成单步频率调整作为输出。生成的单步频率调整被应用于具有第一频率的系统时钟信号，以将系统时钟信号改变为具有第二频率的第二时钟信号。第一频率与第二频率不同，并且系统时钟信号具有在第二时钟信号的第二占空比的容差范围内的第一占空比。

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