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1. 发明申请

US20070033333A1 Non-volatile memory device, and control method of non-volatile memory device 有权
标题翻译：非易失性存储器件，以及非易失性存储器件的控制方法
公开(公告)号：US20070033333A1
公开(公告)日：2007-02-08
申请号：US11479387
申请日：2006-06-30
申请人： Kenta Kato , Mitsuhiro Nagao
发明人： Kenta Kato , Mitsuhiro Nagao
IPC分类号： G06F12/00
CPC分类号： G11C16/0416 , G11C16/22
摘要： In a memory cell array, aside from a normal-data storing region, a control-information storing region is also allocated, and the control-information storing region is composed of a predetermined number of control-information storing memory cells in each bit of control information, and same bit data is stored in the predetermined number of control-information storing memory cells, and the data is read out simultaneously at the time of reading out. When being read-out the control information, since data is read out simultaneously from the predetermined number of memory cells, the driving capacity of reading route when reading out is reinforced. Reading time of control information being read out at the time of turning on the power or initializing after resetting can be shortened, and the operation can be quickly transferred to normal access action.
摘要翻译：在存储单元阵列中，除了正常数据存储区域之外，还分配控制信息存储区域，并且控制信息存储区域由预定数量的控制信息组成，每个控制位存储存储单元信息和相同位数据被存储在预定数量的控制信息存储单元中，并且在读出时同时读出数据。当读出控制信息时，由于从预定数量的存储单元同时读出数据，所以读出时读取路径的驱动能力得到加强。可以缩短在开启电源或复位后的初始化时读取的控制信息的读取时间，并且可以快速地将操作转移到正常的访问动作。

2. 发明申请

US20060101301A1 Non-volatile memory device 有权
标题翻译：非易失性存储器件
公开(公告)号：US20060101301A1
公开(公告)日：2006-05-11
申请号：US11259874
申请日：2005-10-26
申请人： Mitsuhiro Nagao , Kenta Kato
发明人： Mitsuhiro Nagao , Kenta Kato
IPC分类号： G06F1/04
CPC分类号： G11C7/20 , G11C7/24 , G11C8/08 , G11C11/417 , G11C16/20 , G11C16/225 , G11C29/028 , G11C2029/4402
摘要： The operational information read out by the read-out sense amplifier (19) is transferred via the data line DB to a volatile memory section. The volatile memory section is configured with the volatile memory section (21) having a SRAM configuration and the second volatile memory section (23) configured with latch circuits, which are respectively connected in parallel with the data line DB. The operational information, which may be provided depending on an operation state of the write-protect information and other information stored in the non-volatile memory cell MC selected by the word line WLWP, is written and read out with respect to the first volatile memory section (21) in response to the identification information linked with the operational information. The operational information which must be constantly accessible, is written into the second volatile memory section (23) in response to the identification information. Thus, the operational information is available in a memory mode depending on the attributes of the operational information.
摘要翻译：由读出放大器（19）读出的运算信息经由数据线DB传送到易失性存储器部分。易失性存储器部分配置有具有SRAM配置的易失性存储器部分（21）和配置有分别与数据线DB并联连接的锁存电路的第二易失性存储器部分（23）。可以根据写保护信息的操作状态和由字线WLWP选择的存储在非易失性存储单元MC中的其他信息提供的操作信息相对于第一易失性存储器被写入和读出部分（21）响应于与操作信息相关联的识别信息。响应于识别信息，必须始终可访问的操作信息被写入第二易失性存储器部分（23）。因此，根据操作信息的属性，操作信息以存储模式可用。

3. 发明申请

US20060044877A1 Non-volatile memory device, and control method therefor 有权
标题翻译：非易失性存储器件及其控制方法
公开(公告)号：US20060044877A1
公开(公告)日：2006-03-02
申请号：US11215850
申请日：2005-08-30
申请人： Kenta Kato
发明人： Kenta Kato
IPC分类号： G11C16/04
CPC分类号： G11C16/12 , G11C8/08 , G11C16/08 , G11C16/14
摘要： During an erase operation, lower decoder groups 20(i) and 21(i) (i=1 to m) of erase-target sectors are connected, at their respective low voltage power supply terminals (VL), to a first negative voltage supply line (VM) via switches (B) (50 and 51, respectively) and a negative bias voltage is supplied to local word lines. The first negative voltage supply line (VM) is connected to a level shift circuit (4), and is level-shifted to a voltage at a higher level relative to that of a second negative voltage (VMP) which is output from a negative voltage generator circuit (3) via a second negative voltage supply line (VMP). An upper decoder group (10) is connected, at its low voltage power supply terminal (VL), to the second negative voltage line (VMP) via a switch (A) (5). All global word lines GWL0(i) (i=0 to m) are biased to the second negative voltage (VMP) by an active signal (ACTB0(i)) at high level supplied to the upper decoder group (10) and are biased to a lower voltage level relative to the first negative voltage (VM) as a bias voltage to the local word lines.
摘要翻译：在擦除操作期间，擦除目标扇区的低解码器组20（i）和21（i）（i = 1到m）在其各自的低电压电源端子（VL）处连接到第一负电压源线路（VM）分别通过开关（B）（50和51），负偏置电压被提供给本地字线。第一负电压供给线（VM）连接到电平移位电路（4），并且相对于从负电压（VMP）输出的第二负电压（VMP）的电平被电平移位到较高电平发电机电路（3）经由第二负电压供给线（VMP）。上解码器组（10）通过开关（A）（5）在其低压电源端子（VL）处连接到第二负电压线（VMP）。通过提供给上层解码器组（10）的高电平的有效信号（ACTB 0（i））将所有全局字线GWL 0（i）（i = 0至m）偏置到第二负电压（VMP），以及被偏置到相对于第一负电压（VM）的较低电压电平作为对本地字线的偏置电压。

4. 发明申请

US20060023508A1 Method and apparatus for information setting in a non-volatile memory device 有权
标题翻译：用于在非易失性存储器件中设置信息的方法和装置
公开(公告)号：US20060023508A1
公开(公告)日：2006-02-02
申请号：US11192562
申请日：2005-07-29
申请人： Satoru Sugimoto , Kenta Kato
发明人： Satoru Sugimoto , Kenta Kato
IPC分类号： G11C14/00
CPC分类号： G11C7/24 , G11C7/1078 , G11C7/109 , G11C16/06 , G11C16/22
摘要： In inputting control information for setting access conditions in a system having a common data bus (3), when a predetermined bit string making up an access condition setting command is inputted to predetermined terminals which are not data input/output terminals (S3), the predetermined terminals are set as control information input terminals (S5) and inputted control information is temporarily maintained in a non-volatile memory device (S13). When inputting of control information is completed (S15), the control information that has been temporarily maintained is stored in a non-volatile memory region all at once (S17). During an access condition setting operation, the data input/output terminals are released (S7) and the data bus (3) is made available to other banks or devices (2) so that data transfer efficiency of the system can be improved.
摘要翻译：在输入具有公用数据总线（3）的系统中设定存取条件的控制信息时，当构成存取条件设定指令的规定位串被输入到不是数据输入输出端子的规定端子（S 3）时，将预定端子设置为控制信息输入端子（S 5），并将输入的控制信息暂时保持在非易失性存储器件中（S13）。当完成控制信息的输入（S15）时，暂时保持的控制信息一次存储在非易失性存储区域（S17）。在访问条件设置操作期间，释放数据输入/输出端子（S7），使数据总线（3）可用于其他存储体或设备（2），从而可以提高系统的数据传输效率。

5. 发明授权

US06975540B2 Semiconductor memory device for differential data amplification and method therefor 有权
标题翻译：用于差分数据放大的半导体存储器件及其方法
公开(公告)号：US06975540B2
公开(公告)日：2005-12-13
申请号：US10614066
申请日：2003-07-08
申请人： Kenta Kato
发明人： Kenta Kato
IPC分类号： G11C16/04 , G11C7/06 , G11C7/14 , G11C16/28 , G11C16/06
CPC分类号： G11C7/14 , G11C7/062 , G11C7/067 , G11C16/28
摘要： It is intended to provide a semiconductor memory device capable of making margin of readout operation constant regardless of any selected memory cells wherein the number of reference cells is restrained to minimum essential number and reference current value of which depends on a selected memory cell is obtained. A memory cell selected by address Y(X) is connected to a data line DB and data in the memory cell is read out from a memory cell array 3. Then, a differential amplifier 4 amplifies the data with reference to a reference value supplied to a reference line RB from a reference section 2. The reference section 2 is constituted by a reference cell RC and a source resistance adjustor section 1 that is connected to a source terminal of the reference cell RC. A load adjustor section 1 adjusts a resistance value that is connected to the source terminal of the reference cell RC by the address Y(X). A source resistance adjustor section 1 connects a load equivalent to a load selected by a memory cell in accordance with the address Y(X) to the reference cell RC, whereby an appropriate reference value is constantly supplied.
摘要翻译：旨在提供一种能够使读出操作余量恒定的半导体存储器件，而不管任何选择的存储单元，其中参考单元的数量被限制到最小基本数，并且其参考电流值取决于所选存储单元。由地址Y（X）选择的存储单元连接到数据线DB，并且从存储单元阵列3读出存储单元中的数据。然后，差分放大器4参照提供给来自参考部分2的参考线路RB。参考部分2由参考单元RC和源电阻调节器部分1构成，源极电阻调节器部分1连接到参考单元RC的源极端子。负载调整部1通过地址Y（X）调整与参考单元RC的源极端子连接的电阻值。源极电阻调节器部分1将等效于由存储器单元选择的负载根据地址Y（X）连接到参考单元RC，从而恒定地提供适当的参考值。

6. 发明申请

US20080155217A1 Semiconductor device and method of controlling the same 有权
标题翻译：半导体装置及其控制方法
公开(公告)号：US20080155217A1
公开(公告)日：2008-06-26
申请号：US11644161
申请日：2006-12-22
申请人： Kenta Kato , Masahiko Okura , Kenji Shibata , Mitsuhiro Nagao , Stewart Wang
发明人： Kenta Kato , Masahiko Okura , Kenji Shibata , Mitsuhiro Nagao , Stewart Wang
IPC分类号： G06F12/14
CPC分类号： G06F12/1425 , G06F2212/2022
摘要： A semiconductor device includes: a memory cell array that includes non-volatile memory cells; a first memory region and a second memory region that are located in the memory cell array, the first memory region being protected during a protecting period, the second memory region being not protected; an address change circuit that changes an address in an address space of the first memory region and the second memory region in the memory cell array, to an address in an address space of the second memory region, during the protecting period; and a control circuit that prohibits access to the first memory region, and allows access to the second region, during the protecting period.
摘要翻译：半导体器件包括：包括非易失性存储器单元的存储单元阵列; 位于所述存储单元阵列中的第一存储器区域和第二存储器区域，所述第一存储器区域在保护期间被保护，所述第二存储器区域不被保护; 在保护期间，将存储单元阵列中的第一存储器区域和第二存储器区域的地址空间中的地址改变为第二存储器区域的地址空间中的地址的地址改变电路; 以及控制电路，其在保护期间禁止对第一存储区域的访问，并允许访问第二区域。

7. 发明申请

US20060250167A1 Voltage detection circuit, semiconductor device, method for controlling voltage detection circuit 有权
公开(公告)号：US20060250167A1
公开(公告)日：2006-11-09
申请号：US11482129
申请日：2006-07-07
申请人： Kenta Kato , Satoru Kawamoto
发明人： Kenta Kato , Satoru Kawamoto
IPC分类号： H03K5/22
CPC分类号： H03K5/08 , G01R19/16519 , G11C5/143 , G11C16/30
摘要： A voltage detection circuit for accurately detecting a voltage while suppressing the voltage fluctuation due to the off-leak current of a transistor. The voltage detection circuit includes first and second capacitors, first and second transistors, a comparator, and a control circuit. The capacitors are connected in series to generate a division voltage corresponding to a high voltage by the capacitors. The potential at a node between the first capacitor and the second capacitor is reset to ground potential when the transistors are activated. When the potential at the node reaches a predetermined potential, the first transistor is inactivated, and then the second transistor is inactivated.

8. 发明授权

US08443131B2 Non-volatile memory device 有权
标题翻译：非易失性存储器件
公开(公告)号：US08443131B2
公开(公告)日：2013-05-14
申请号：US11259874
申请日：2005-10-26
申请人： Mitsuhiro Nagao , Kenta Kato
发明人： Mitsuhiro Nagao , Kenta Kato
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28 , G11C11/34 , G11C16/04 , G11C7/10
CPC分类号： G11C7/20 , G11C7/24 , G11C8/08 , G11C11/417 , G11C16/20 , G11C16/225 , G11C29/028 , G11C2029/4402
摘要： Operational information read out by a read-out sense amplifier (19) is transferred via the data line DB to a volatile memory section. The volatile memory section is configured with the volatile memory section (21) having a SRAM configuration and the second volatile memory section (23) configured with latch circuits, both sections respectively connected in parallel with the data line DB. The operational information, which may be provided depending on an operation state of the write-protect information and other information stored in the non-volatile memory cell MC selected by the word line WLWP, is written and read out with respect to the first volatile memory section (21) in response to the identification information linked with the operational information. The operational information which must be constantly accessible, is written into the second volatile memory section (23). Thus, the operational information is available in response to attributes of the operational information.
摘要翻译：由读出放大器（19）读出的操作信息经由数据线DB传送到易失性存储器部分。易失性存储器部分配置有具有SRAM配置的易失性存储器部分（21）和配置有锁存电路的第二易失性存储器部分（23），两个部分分别与数据线DB并联连接。可以根据写保护信息的操作状态和由字线WLWP选择的存储在非易失性存储单元MC中的其他信息提供的操作信息相对于第一易失性存储器被写入和读出部分（21）响应于与操作信息相关联的识别信息。必须经常访问的操作信息被写入第二易失性存储器部分（23）。因此，响应于操作信息的属性，操作信息可用。

9. 发明申请

US20100329003A1 MEMORY EMPLOYING INDEPENDENT DYNAMIC REFERENCE AREAS 有权
标题翻译：使用独立动态参考区域的记忆
公开(公告)号：US20100329003A1
公开(公告)日：2010-12-30
申请号：US12494114
申请日：2009-06-29
申请人： Kenta Kato , Masahiro Niimi , Koji Shimbayashi
发明人： Kenta Kato , Masahiro Niimi , Koji Shimbayashi
IPC分类号： G11C16/06 , G11C7/02
CPC分类号： G11C16/28 , G11C7/14
摘要： A memory that employs separate Dref areas that are independently accessed to provide a threshold voltage reference signal. The memory includes the separate Dref areas, a data area positioned between the Dref areas, one or more sense amplifiers, and a switch component. The switch component is arranged to receive addressing data and to independently couple one of the separate Dref areas to the sense amplifiers based, at least in part, on a physical proximity of individual memory cells along a word line.
摘要翻译：采用独立访问的独立Dref区域以提供阈值电压参考信号的存储器。存储器包括单独的Dref区域，位于Dref区域之间的数据区域，一个或多个读出放大器和开关组件。开关部件布置成接收寻址数据，并且至少部分地基于单个存储器单元沿着字线的物理接近度将独立的Dref区域独立地耦合到读出放大器。

10. 发明授权

US07633824B2 Charge pump to supply voltage bands 失效
标题翻译：电荷泵供电电压带
公开(公告)号：US07633824B2
公开(公告)日：2009-12-15
申请号：US12012389
申请日：2008-02-01
申请人： Kenta Kato
发明人： Kenta Kato
IPC分类号： G11C5/14
CPC分类号： H02M3/07 , G11C16/30
摘要： The present invention provides a voltage generating circuit and a control method thereof which is capable of preventing an increase in the occupied area and suitable for raising the voltage of the power supply in a wide range.This voltage generating circuit comprises a first charge pump unit to which a first clock signal is inputted, wherein the first charge pump unit generates a voltage by pumping a voltage of a first external power supply in stages by a first voltage, a voltage selector that selects the voltage generated by the first charge pump unit or a voltage of a second external power supply in accordance with a voltage selection command signal, a level converter that converts a voltage level of the first clock signal into a second voltage level, and a second charge pump unit to which the second clock signal that has been converted by the level converter is inputted, wherein the second charge pump unit and that generates a voltage and by pumping the selected voltage or the voltage of the second external power supply.
摘要翻译：本发明提供一种电压产生电路及其控制方法，其能够防止占用面积的增加并且适合于在宽范围内提高电源的电压。该电压产生电路包括输入第一时钟信号的第一电荷泵单元，其中第一电荷泵单元通过以第一电压分阶段地泵浦第一外部电源的电压来产生电压;电压选择器，其选择由第一电荷泵单元产生的电压或根据电压选择指令信号的第二外部电源的电压，将第一时钟信号的电压电平转换为第二电压电平的电平转换器和第二电荷其中输入了由电平转换器转换的第二时钟信号的泵单元，其中第二电荷泵单元产生电压并通过泵浦所选择的电压或第二外部电源的电压。

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