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1. 发明授权

US08440575B2 Method of fabricating semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US08440575B2
公开(公告)日：2013-05-14
申请号：US13523351
申请日：2012-06-14
申请人： Kensuke Taniguchi
发明人： Kensuke Taniguchi
IPC分类号： H01L21/302
CPC分类号： H01L21/76224 , H01L21/0338 , H01L21/31116 , H01L21/32139 , H01L21/823481
摘要： A method includes: forming an device isolation region in a substrate to divide the device isolation region into first and second diffusion regions; forming a target film on the substrate; forming a hard mask layer and a first resist layer on the film; forming a first pattern on the first resist layer; etching the hard mask layer by using the first pattern as a mask; forming a second resist layer on the hard mask layer; forming a second pattern including a first space on the second resist layer for isolating the first pattern; forming a third pattern including a second space shrunk from the first space on the hard mask layer by carrying out size conversion etching by using the second pattern formed on the second resist layer as a mask; and etching the film to be processed by using the third pattern formed on the hard mask layer.
摘要翻译：一种方法包括：在衬底中形成器件隔离区以将器件隔离区分成第一和第二扩散区; 在基板上形成靶膜; 在膜上形成硬掩模层和第一抗蚀剂层; 在所述第一抗蚀剂层上形成第一图案; 通过使用第一图案作为掩模蚀刻硬掩模层; 在所述硬掩模层上形成第二抗蚀剂层; 在所述第二抗蚀剂层上形成包括第一空间以隔离所述第一图案的第二图案; 通过使用形成在第二抗蚀剂层上的第二图案作为掩模，通过进行尺寸转换蚀刻，形成包括从硬掩模层上的第一空间收缩的第二空间的第三图案; 并且通过使用形成在硬掩模层上的第三图案来蚀刻待处理的膜。

2. 发明授权

US08124542B2 Method of fabricating semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08124542B2
公开(公告)日：2012-02-28
申请号：US12205950
申请日：2008-09-08
申请人： Kensuke Taniguchi
发明人： Kensuke Taniguchi
IPC分类号： H01L21/302
CPC分类号： H01L21/76224 , H01L21/0338 , H01L21/31116 , H01L21/32139 , H01L21/823481
摘要： The present invention includes the steps of: forming an device isolation region in a substrate to divide the device isolation region into a first and a second diffusion regions; forming a target film to be processed on the substrate; forming a hard mask layer and a first resist layer on the film to be processed; forming a first pattern on the first resist layer; etching the hard mask layer by using the first pattern as a mask; forming a second resist layer on the hard mask layer; forming a second pattern including a first space on the second resist layer for isolating the first pattern; forming a third pattern including a second space shrunk from the first space on the hard mask layer by carrying out size conversion etching by using the second pattern formed on the second resist layer as a mask; and etching the film to be processed by using the third pattern formed on the hard mask layer.
摘要翻译：本发明包括以下步骤：在衬底中形成器件隔离区以将器件隔离区分成第一和第二扩散区; 在基板上形成待加工的靶膜; 在待加工的膜上形成硬掩模层和第一抗蚀剂层; 在所述第一抗蚀剂层上形成第一图案; 通过使用第一图案作为掩模蚀刻硬掩模层; 在所述硬掩模层上形成第二抗蚀剂层; 在所述第二抗蚀剂层上形成包括第一空间以隔离所述第一图案的第二图案; 通过使用形成在第二抗蚀剂层上的第二图案作为掩模，通过进行尺寸转换蚀刻，形成包括从硬掩模层上的第一空间收缩的第二空间的第三图案; 并且通过使用形成在硬掩模层上的第三图案来蚀刻待处理的膜。

3. 发明授权

US07462566B2 Method for manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US07462566B2
公开(公告)日：2008-12-09
申请号：US11600071
申请日：2006-11-16
申请人： Masato Fujita , Kensuke Taniguchi , Akira Mitsuiki
发明人： Masato Fujita , Kensuke Taniguchi , Akira Mitsuiki
IPC分类号： H01L21/302
CPC分类号： H01L21/32139 , H01L21/0337 , H01L21/28035
摘要： In the process of forming a predetermined pattern in a process target film, a stacked hard mask film having a first film, a second film and a third film stacked in this order is formed on the process target film (S100), fine line patterns are formed in the third film through a fine-pattern-forming resist film while using the second film as an etching stopper (S102), and the fine-pattern-forming resist film is removed (S104). Subsequently, light exposure is carried out using a resist film (S106 to S110), and the second film, the first film and the process target film are then selectively dry-etched in a sequential manner, to thereby form the process target film into a predetermined pattern (S112). The first film remained on the process target film is then removed (S114).
摘要翻译：在处理目标薄膜中形成预定图案的过程中，在处理目标薄膜上形成具有第一薄膜，第二薄膜和第三薄膜的层叠的硬掩模薄膜（S100），细线图案是通过精细图案形成抗蚀剂膜形成在第三膜中，同时使用第二膜作为蚀刻停止层（S102），除去微细图案形成抗蚀剂膜（S104）。随后，使用抗蚀剂膜进行曝光（S106〜S110），然后依次对第二膜，第一膜和处理对象膜进行选择性干蚀刻，从而将处理目标膜形成为预定图案（S112）。然后，将残留在处理目标膜上的第一膜除去（S114）。

4. 发明授权

US09604012B2 Barrel with cap, pre-filled syringe, and cap with connector 有权
公开(公告)号：US09604012B2
公开(公告)日：2017-03-28
申请号：US14009582
申请日：2011-04-20
申请人： Taiji Horita , Norihiko Asahi , Ippei Matsumoto , Kensuke Taniguchi , Takeshi Karasawa , Akemi Sasaki
发明人： Taiji Horita , Norihiko Asahi , Ippei Matsumoto , Kensuke Taniguchi , Takeshi Karasawa , Akemi Sasaki
IPC分类号： A61M5/34 , A61M5/31
CPC分类号： A61M5/344 , A61M5/347 , A61M2005/3104
摘要： A barrel with a cap, a pre-filled syringe, and a cap with a connector that accommodate connection-receiving bodies of the Luer lock type and of the slip-in type, are provided. Some versions include: a connector (3) detachably coupled to a cap (2) so as to be separated from the barrel (1) together with the cap (2) when the connector (3) is located at an initial position where the connector (3) is attached to a barrel (1) via the cap (2); and a connector-side engaging part (33) that engages a barrel-side engaging part (13) of the barrel (1) when the connector (3) is located at an attached position that is closer to a proximal end in an axial direction of the barrel (1) than the initial position, allowing the connector (3) to remain attached to the barrel (1) by being detached from the cap (2) separated from a nozzle (11).

5. 发明申请

US20120276708A1 METHOD OF FABRICATING SEMICONDUCTOR DEVICE 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US20120276708A1
公开(公告)日：2012-11-01
申请号：US13523351
申请日：2012-06-14
申请人： Kensuke TANIGUCHI
发明人： Kensuke TANIGUCHI
IPC分类号： H01L21/768 , H01L21/76
CPC分类号： H01L21/76224 , H01L21/0338 , H01L21/31116 , H01L21/32139 , H01L21/823481
摘要： A method includes: forming an device isolation region in a substrate to divide the device isolation region into first and second diffusion regions; forming a target film on the substrate; forming a hard mask layer and a first resist layer on the film; forming a first pattern on the first resist layer; etching the hard mask layer by using the first pattern as a mask; forming a second resist layer on the hard mask layer; forming a second pattern including a first space on the second resist layer for isolating the first pattern; forming a third pattern including a second space shrunk from the first space on the hard mask layer by carrying out size conversion etching by using the second pattern formed on the second resist layer as a mask; and etching the film to be processed by using the third pattern formed on the hard mask layer.
摘要翻译：一种方法包括：在衬底中形成器件隔离区以将器件隔离区分成第一和第二扩散区; 在基板上形成靶膜; 在膜上形成硬掩模层和第一抗蚀剂层; 在所述第一抗蚀剂层上形成第一图案; 通过使用第一图案作为掩模蚀刻硬掩模层; 在所述硬掩模层上形成第二抗蚀剂层; 在所述第二抗蚀剂层上形成包括第一空间以隔离所述第一图案的第二图案; 通过使用形成在第二抗蚀剂层上的第二图案作为掩模，通过进行尺寸转换蚀刻，形成包括从硬掩模层上的第一空间收缩的第二空间的第三图案; 并且通过使用形成在硬掩模层上的第三图案来蚀刻待处理的膜。

6. 发明申请

US20080085608A1 Method for manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20080085608A1
公开(公告)日：2008-04-10
申请号：US11600071
申请日：2006-11-16
申请人： Masato Fujita , Kensuke Taniguchi , Akira Mitsuiki
发明人： Masato Fujita , Kensuke Taniguchi , Akira Mitsuiki
IPC分类号： H01L21/31
CPC分类号： H01L21/32139 , H01L21/0337 , H01L21/28035
摘要： In the process of forming a predetermined pattern in a process target film, a stacked hard mask film having a first film, a second film and a third film stacked in this order is formed on the process target film (S100), fine line patterns are formed in the third film through a fine-pattern-forming resist film while using the second film as an etching stopper (S102), and the fine-pattern-forming resist film is removed (S104). Subsequently, light exposure is carried out using a resist film (S106 to S110), and the second film, the first film and the process target film are then selectively dry-etched in a sequential manner, to thereby form the process target film into a predetermined pattern (S112). The first film remained on the process target film is then removed (S114).
摘要翻译：在处理目标薄膜中形成预定图案的过程中，在工艺目标薄膜（S100）上形成具有第一薄膜，第二薄膜和第三薄膜的层叠的硬掩膜，通过精细图案形成抗蚀剂膜形成在第三膜中，同时使用第二膜作为蚀刻停止层（S102），除去微细图案形成抗蚀剂膜（S104）。随后，使用抗蚀剂膜（S106〜S110）进行曝光，然后依次对第二膜，第一膜和处理对象膜进行选择性干蚀刻，从而形成处理对象膜变成预定图案（S112）。然后将剩余在工艺靶膜上的第一膜除去（S114）。

7. 发明申请

US20140025017A1 BARREL WITH CAP, PRE-FILLED SYRINGE, AND CAP WITH CONNECTOR 有权
标题翻译：带盖帽，预先灌装的塞子和带连接器的盖子
公开(公告)号：US20140025017A1
公开(公告)日：2014-01-23
申请号：US14009582
申请日：2011-04-20
申请人： Taiji Horita , Norihiko Asahi , Ippei Matsumoto , Kensuke Taniguchi , Takeshi Karasawa , Akemi Sasaki
发明人： Taiji Horita , Norihiko Asahi , Ippei Matsumoto , Kensuke Taniguchi , Takeshi Karasawa , Akemi Sasaki
IPC分类号： A61M5/34
CPC分类号： A61M5/344 , A61M5/347 , A61M2005/3104
摘要： The present invention provides a barrel with a cap, a pre-filled syringe, and a cap with a connector that are available for both connection-receiving bodies of the Luer lock type and connection-receiving bodies of the slip-in type. The present invention is characterized by including: a connector (3) that is detachably coupled to a cap (2) so as to be separated from the barrel (1) together with the cap (2) when the connector (3) is located at an initial position where the connector (3) is attached to a barrel (1) via the cap (2); and a connector-side engaging part 33 that engages a barrel-side engaging part (13) of the barrel (1) when the connector (3) is located at an attached position that is located closer to a proximal end in an axial direction of the barrel (1) than the initial position is, thereby allowing the connector (3) to remain attached to the barrel (1) by being detached from the cap (2) separated from a nozzle (11).
摘要翻译：本发明提供一种具有盖，预填充注射器和具有连接器的盖，其可用于Luer锁式连接接收体和滑入式连接接收体两者。本发明的特征在于包括：连接器（3），其可拆卸地联接到帽（2），以便当连接器（3）位于（1）处时，与盖（2）一起与盖连接器（3）经由盖（2）附接到枪管（1）的初始位置; 以及连接器侧接合部33，其在所述连接器（3）位于所述连接器（3）位于更靠近基端的安装位置时与所述筒体（1）的筒体侧接合部（13）接合，桶（1）比起初始位置为止，从而允许连接器（3）通过从与喷嘴（11）分离的盖（2）分离而保持附接到筒体（1）。

8. 发明授权

US08202802B2 Method of fabricating semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US08202802B2
公开(公告)日：2012-06-19
申请号：US13328331
申请日：2011-12-16
申请人： Kensuke Taniguchi
发明人： Kensuke Taniguchi
IPC分类号： H01L21/44
CPC分类号： H01L21/76224 , H01L21/0338 , H01L21/31116 , H01L21/32139 , H01L21/823481
摘要： The present method includes: forming a device isolation region in a substrate dividing the device isolation region into first and second diffusion regions; forming a target film to be processed on the substrate; forming a hard mask layer and a first resist layer on the film; forming a first pattern on the first resist layer; etching the hard mask layer using the first pattern as a mask; forming a second resist layer on the hard mask layer; forming a second pattern including a first space on the second resist layer isolating the first pattern; forming a third pattern including a second space shrunk from the first space on the hard mask layer by carrying out size conversion etching by using the second pattern formed on the second resist layer as a mask; and etching the film to be processed by using the third pattern formed on the hard mask layer.
摘要翻译：本方法包括：在将器件隔离区域分成第一和第二扩散区域的衬底中形成器件隔离区域; 在基板上形成待加工的靶膜; 在膜上形成硬掩模层和第一抗蚀剂层; 在所述第一抗蚀剂层上形成第一图案; 使用第一图案作为掩模蚀刻硬掩模层; 在所述硬掩模层上形成第二抗蚀剂层; 形成包括在所述第二抗蚀剂层上的第一空间的第二图案，隔离所述第一图案; 通过使用形成在第二抗蚀剂层上的第二图案作为掩模，通过进行尺寸转换蚀刻，形成包括从硬掩模层上的第一空间收缩的第二空间的第三图案; 并且通过使用形成在硬掩模层上的第三图案来蚀刻待处理的膜。

9. 发明申请

US20090068826A1 METHOD OF FABRICATING SEMICONDUCTOR DEVICE 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20090068826A1
公开(公告)日：2009-03-12
申请号：US12205950
申请日：2008-09-08
申请人： Kensuke TANIGUCHI
发明人： Kensuke TANIGUCHI
IPC分类号： H01L21/467
CPC分类号： H01L21/76224 , H01L21/0338 , H01L21/31116 , H01L21/32139 , H01L21/823481
摘要： The present invention includes the steps of: forming an device isolation region in a substrate to divide the device isolation region into a first and a second diffusion regions; forming a target film to be processed on the substrate; forming a hard mask layer and a first resist layer on the film to be processed; forming a first pattern on the first resist layer; etching the hard mask layer by using the first pattern as a mask; forming a second resist layer on the hard mask layer; forming a second pattern including a first space on the second resist layer for isolating the first pattern; forming a third pattern including a second space shrunk from the first space on the hard mask layer by carrying out size conversion etching by using the second pattern formed on the second resist layer as a mask; and etching the film to be processed by using the third pattern formed on the hard mask layer.
摘要翻译：本发明包括以下步骤：在衬底中形成器件隔离区以将器件隔离区分成第一和第二扩散区; 在基板上形成待加工的靶膜; 在待加工的膜上形成硬掩模层和第一抗蚀剂层; 在所述第一抗蚀剂层上形成第一图案; 通过使用第一图案作为掩模蚀刻硬掩模层; 在所述硬掩模层上形成第二抗蚀剂层; 在所述第二抗蚀剂层上形成包括第一空间以隔离所述第一图案的第二图案; 通过使用形成在第二抗蚀剂层上的第二图案作为掩模，通过进行尺寸转换蚀刻，形成包括从硬掩模层上的第一空间收缩的第二空间的第三图案; 并且通过使用形成在硬掩模层上的第三图案来蚀刻待处理的膜。

10. 发明申请

US20120276709A1 METHOD OF FABRICATING SEMICONDUCTOR DEVICE 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：US20120276709A1
公开(公告)日：2012-11-01
申请号：US13523482
申请日：2012-06-14
申请人： Kensuke TANIGUCHI
发明人： Kensuke TANIGUCHI
IPC分类号： H01L21/768 , H01L21/76
CPC分类号： H01L21/76224 , H01L21/0338 , H01L21/31116 , H01L21/32139 , H01L21/823481
摘要： A method includes: forming an device isolation region in a substrate to divide the device isolation region into a first and a second diffusion regions; forming a target film on the substrate; forming a hard mask layer and a first resist layer on the film; forming a first pattern on the first resist layer; etching the hard mask layer using the first pattern as a mask; forming a second resist layer on the hard mask layer; forming a second pattern including a first space on the second resist layer for isolating the first pattern; forming a third pattern including a second space shrunk from the first space on the hard mask layer by carrying out size conversion etching by using the second pattern formed on the second resist layer as a mask; and etching the film to be processed by using the third pattern formed on the hard mask layer.
摘要翻译：一种方法包括：在衬底中形成器件隔离区以将器件隔离区分成第一和第二扩散区; 在基板上形成靶膜; 在膜上形成硬掩模层和第一抗蚀剂层; 在所述第一抗蚀剂层上形成第一图案; 使用第一图案作为掩模蚀刻硬掩模层; 在所述硬掩模层上形成第二抗蚀剂层; 在所述第二抗蚀剂层上形成包括第一空间以隔离所述第一图案的第二图案; 通过使用形成在第二抗蚀剂层上的第二图案作为掩模，通过进行尺寸转换蚀刻，形成包括从硬掩模层上的第一空间收缩的第二空间的第三图案; 并且通过使用形成在硬掩模层上的第三图案来蚀刻待处理的膜。

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