专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07666761B2 Semiconductor device and manufacturing method thereof 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US07666761B2
公开(公告)日：2010-02-23
申请号：US11680814
申请日：2007-03-01
申请人： Kiyonori Oyu , Kensuke Okonogi , Hirotaka Kobayashi , Koji Hamada
发明人： Kiyonori Oyu , Kensuke Okonogi , Hirotaka Kobayashi , Koji Hamada
IPC分类号： H01L21/322
CPC分类号： H01L21/3221 , H01L21/304
摘要： In manufacturing a semiconductor device, the first gettering layer is formed on the backside of a wafer, and the second gettering layers are then formed on the backside and side surfaces of a chip, allowing these gettering layers to serve as trapping sites against metallic contamination that generated after backside grinding in assembly processes.
摘要翻译：在制造半导体器件时，第一吸气层形成在晶片的背面，然后第二吸气层形成在芯片的背面和侧表面上，允许这些吸气层用作捕获位置以抵抗金属污染，在组装过程中后侧研磨后产生。

2. 发明申请

US20080230845A1 SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME 有权
标题翻译：半导体器件及其形成方法
公开(公告)号：US20080230845A1
公开(公告)日：2008-09-25
申请号：US11859043
申请日：2007-09-21
申请人： Kensuke Okonogi , Kiyonori Ohyu
发明人： Kensuke Okonogi , Kiyonori Ohyu
IPC分类号： H01L29/78 , H01L23/52 , H01L21/4763
CPC分类号： H01L29/7834 , H01L21/26506 , H01L21/28525 , H01L21/76843 , H01L21/76859 , H01L23/53271 , H01L29/66628 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device may include, but is not limited to, a single crystal silicon diffusion layer, a polycrystal silicon conductor, and a diffusion barrier layer. The diffusion barrier layer separates the polycrystal silicon conductor from the single crystal silicon diffusion layer. The diffusion barrier layer prevents a diffusion of at least one of silicon-interstitial and silicon-vacancy between the single crystal silicon diffusion layer and the polycrystal silicon conductor.
摘要翻译：半导体器件可以包括但不限于单晶硅扩散层，多晶硅导体和扩散阻挡层。扩散阻挡层将多晶硅导体与单晶硅扩散层分离。扩散阻挡层防止在单晶硅扩散层和多晶硅导体之间的硅间隙和硅空位中的至少一个的扩散。

3. 发明授权

US07186632B2 Method of fabricating a semiconductor device having a decreased concentration of phosphorus impurities in polysilicon 失效
标题翻译：制造在多晶硅中磷杂质浓度降低的半导体器件的方法
公开(公告)号：US07186632B2
公开(公告)日：2007-03-06
申请号：US10395724
申请日：2003-03-24
申请人： Kazuo Ogawa , Kiyonori Ohyu , Kensuke Okonogi , Toshihiro Imamura , Keiichi Watanabe , Hiroyuki Ohta
发明人： Kazuo Ogawa , Kiyonori Ohyu , Kensuke Okonogi , Toshihiro Imamura , Keiichi Watanabe , Hiroyuki Ohta
IPC分类号： H01L21/3205 , H01L21/4763
CPC分类号： H01L21/28247 , H01L21/28061
摘要： In a method for manufacturing a semiconductor device having a laminated gate electrode, a phosphorus-doped polysilicon is formed on a gate oxide film. A high-melting metal or a compound of a high-melting metal and silicon is formed on the polysilicon. Phosphorus is doped into the polysilicon so that a concentration of the phosphorus in the polysilicon at an interface between the polysilicon and the gate oxide film is 2×1020(1/cm3) or less. Then, thermal oxidation is carried out in a wet-hydrogen atmosphere containing water vapor.
摘要翻译：在具有层叠栅电极的半导体器件的制造方法中，在栅极氧化膜上形成磷掺杂多晶硅。在多晶硅上形成高熔点金属或高熔点金属和硅的化合物。将磷掺杂到多晶硅中，使得多晶硅和栅极氧化物膜之间的界面处的多晶硅中的磷的浓度为2×10 20（1 / cm 3）或更少。然后，在含有水蒸气的湿氢气氛中进行热氧化。

4. 发明授权

US07129141B2 Method for manufacturing a semiconductor device having a low junction leakage current 有权
标题翻译：具有低结漏电流的半导体器件的制造方法
公开(公告)号：US07129141B2
公开(公告)日：2006-10-31
申请号：US11024623
申请日：2004-12-30
申请人： Kiyonori Oyu , Kensuke Okonogi
发明人： Kiyonori Oyu , Kensuke Okonogi
IPC分类号： H01L21/336 , H01L21/425
CPC分类号： H01L29/6659 , H01L21/26506 , H01L27/10855 , H01L27/10873
摘要： A method for manufacturing a DRAM device includes the step of implanting phosphor at a specified dosage and heat treating the implanted phosphor for diffusion thereof to form source/drain regions, and implanting fluorine into the source/drain regions and heat treating the implanted fluorine for diffusion thereof. The resultant DRAM memory cell has a larger data storage capability due to lower junction leakage current caused by vacancy type defects formed in the metallurgical junction between the source/drain regions and the channel region.
摘要翻译：一种用于制造DRAM器件的方法包括以特定剂量注入磷光体的步骤，并且对植入的荧光体进行热处理以进行扩散以形成源极/漏极区域，并将氟注入源极/漏极区域并对植入的氟进行热处理以进行扩散其中。由于在源极/漏极区域和沟道区域之间的冶金连接处形成的空位型缺陷引起的较低的结漏电流，所得到的DRAM存储单元具有较大的数据存储能力。

5. 发明授权

US5374582A Laminated substrate for semiconductor device and manufacturing method thereof 失效
标题翻译：半导体装置用层叠基板及其制造方法
公开(公告)号：US5374582A
公开(公告)日：1994-12-20
申请号：US233940
申请日：1994-04-28
申请人： Kensuke Okonogi , Hiroaki Kikuchi
发明人： Kensuke Okonogi , Hiroaki Kikuchi
IPC分类号： H01L21/18 , H01L21/761 , H01L21/762 , H01L21/76
CPC分类号： H01L21/76251 , H01L21/187 , H01L21/761 , Y10S148/012
摘要： A method for fabricating a laminated substrate for a semiconductor device having a high voltage power device and a low voltage element formed in a region isolated from the power device with a P-N junction. The region for the low voltage element is formed on a buried layer of P type formed in the region of N type in which the power device is formed and surrounded by a isolating region of P type reaching the buried layer from the surface of the laminated substrate.
摘要翻译：一种用于制造半导体器件的层压衬底的方法，所述半导体器件具有形成在与具有P-N结的功率器件隔离的区域中的高电压功率器件和低电压元件。低电压元件的区域形成在形成有功率器件的N型区域中形成的P型掩埋层，并且由层叠衬底的表面到达掩埋层的P型隔离区包围。

6. 发明授权

US07338876B2 Method for manufacturing a semiconductor device 失效
标题翻译：半导体器件的制造方法
公开(公告)号：US07338876B2
公开(公告)日：2008-03-04
申请号：US11039857
申请日：2005-01-24
申请人： Kensuke Okonogi , Kiyonori Oyu
发明人： Kensuke Okonogi , Kiyonori Oyu
IPC分类号： H01L21/331
CPC分类号： H01L27/10873 , H01L21/2652 , H01L21/324 , H01L27/10814 , H01L29/6659
摘要： A method for forming a semiconductor memory device includes the steps of: implanting a dopant in a semiconductor substrate; heat treating the semiconductor substrate in an oxidizing ambient to diffuse the dopant for forming diffused regions in the semiconductor substrate; and forming memory cells each including a MOS transistor having the diffused regions as source/drain regions.
摘要翻译：一种用于形成半导体存储器件的方法包括以下步骤：在半导体衬底中注入掺杂剂; 在氧化环境中热处理半导体衬底以扩散掺杂剂以在半导体衬底中形成扩散区域; 以及形成各自包括具有扩散区域的MOS晶体管作为源/漏区的存储单元。

7. 发明授权

US07151033B2 Method for manufacturing a semiconductor device having a low junction leakage current 失效
标题翻译：具有低结漏电流的半导体器件的制造方法
公开(公告)号：US07151033B2
公开(公告)日：2006-12-19
申请号：US11029343
申请日：2005-01-06
申请人： Kiyonori Oyu , Kensuke Okonogi , Koji Hamada
发明人： Kiyonori Oyu , Kensuke Okonogi , Koji Hamada
IPC分类号： H01L21/336 , H01L21/322
CPC分类号： H01L21/3003 , H01L21/324 , H01L27/10814 , H01L27/10873 , H01L29/6659
摘要： A method for manufacturing a DRAM device includes a hydrogenating step conducted to source/drain diffused regions in a hydrogen ambient at a substrate temperature not lower than 350 degrees C., and a dehydrogenating step in an inactive gas ambient at a substrate temperature of lower than 350 degrees C., before a packaging step. If a defective cell having a lower refreshing time is found in the test before the packaging step, the defective cell is replaced by a redundant cell. The resultant DRAM has a lower degradation in the refreshing characteristic after the packaging step.
摘要翻译：一种用于制造DRAM器件的方法包括：在不低于350℃的衬底温度下，在氢环境中对源极/漏极扩散区域进行加氢步骤，以及在低于350℃的衬底温度下的非活性气体环境中的脱氢步骤 350摄氏度，包装步骤之前。如果在包装步骤之前的测试中发现具有较低刷新时间的缺陷单元，则由冗余单元替换缺陷单元。所得的DRAM在包装步骤之后的刷新特性中具有较低的劣化。

8. 发明申请

US20060223292A1 Method of manufacturing semiconductor device 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：US20060223292A1
公开(公告)日：2006-10-05
申请号：US11390138
申请日：2006-03-28
申请人： Kensuke Okonogi , Kiyonori Oyu
发明人： Kensuke Okonogi , Kiyonori Oyu
IPC分类号： H01L21/425
CPC分类号： H01L29/78 , H01L21/823425 , H01L27/10855 , H01L27/10873 , H01L27/10888 , H01L29/1083
摘要： In a method of manufacturing a semiconductor device with a MOS transistor, a channel impurity doped layer of a first conductive type is formed in a silicon substrate. First material is implanted into regions for diffusion layers of a second conductive type as sources/drains of the MOS transistor in the channel impurity doped layer. Heat treatment is carried out after the implanting process of the first material. Then, the diffusion layers are formed in the silicon substrate after the carrying out heat treatment.
摘要翻译：在制造具有MOS晶体管的半导体器件的方法中，在硅衬底中形成第一导电类型的沟道杂质掺杂层。将第一材料注入到作为沟道杂质掺杂层中的MOS晶体管的源极/漏极的第二导电类型的扩散层的区域中。在第一材料的植入过程之后进行热处理。然后，在进行热处理之后，在硅衬底中形成扩散层。

9. 发明申请

US20060084255A1 Semiconductor device and method of manufacturing the same 审中-公开
标题翻译：半导体装置及其制造方法
公开(公告)号：US20060084255A1
公开(公告)日：2006-04-20
申请号：US11246337
申请日：2005-10-11
申请人： Kiyonori Oyu , Kensuke Okonogi
发明人： Kiyonori Oyu , Kensuke Okonogi
IPC分类号： H01L21/4763 , H01L21/336 , H01L21/3205
CPC分类号： H01L21/28114 , H01L21/28044 , H01L29/42376 , H01L29/6659 , H01L29/7833
摘要： A gate dielectric film, a poly-silicon film, a film of a refractory metal such as tungsten, and a gate cap dielectric film are sequentially laminated on a semiconductor substrate. The gate cap dielectric film and the refractory metal film are selectively removed by etching. Thereafter, a double protection film including a silicon nitride film and a silicon oxide film is formed on side surfaces of the gate cap dielectric film, the refractory metal film, and the poly-silicon film. The poly-silicon film is etched using the double protection film as a mask. Thereafter, the semiconductor substrate is light oxidized to form a silicon oxide film on side surfaces of the poly-silicon film. Accordingly, a junction leakage of a MOSFET having a gate electrode of a poly-metal structure, particularly, a memory cell transistor of a DRAM, can be further reduced.
摘要翻译：栅极电介质膜，多晶硅膜，耐火金属如钨的膜和栅极盖电介质膜依次层压在半导体衬底上。通过蚀刻选择性地去除栅极电介质膜和难熔金属膜。此后，在栅极盖电介质膜，难熔金属膜和多晶硅膜的侧表面上形成包括氮化硅膜和氧化硅膜的双重保护膜。使用双重保护膜作为掩模蚀刻多晶硅膜。此后，半导体衬底被光氧化以在多晶硅膜的侧表面上形成氧化硅膜。因此，可以进一步减少具有多金属结构的栅电极，特别是DRAM的存储单元晶体管的MOSFET的结漏电。

10. 发明申请

US20050214973A1 Semiconductor device and manufacturing method thereof 审中-公开
标题翻译：半导体装置及其制造方法
公开(公告)号：US20050214973A1
公开(公告)日：2005-09-29
申请号：US11089461
申请日：2005-03-25
申请人： Kiyonori Oyu , Kensuke Okonogi , Hirotaka Kobayashi , Koji Hamada
发明人： Kiyonori Oyu , Kensuke Okonogi , Hirotaka Kobayashi , Koji Hamada
IPC分类号： H01L21/322 , H01L21/02 , H01L21/302 , H01L21/304 , H01L21/461 , H01L21/50
CPC分类号： H01L21/3221 , H01L21/304
摘要： In manufacturing a semiconductor device, the first gettering layer is formed on the backside of a wafer, and the second gettering layers are then formed on the backside and side surfaces of a chip, allowing these gettering layers to serve as trapping sites against metallic contamination that generated after backside grinding in assembly processes.
摘要翻译：在制造半导体器件时，第一吸气层形成在晶片的背面，然后第二吸气层形成在芯片的背面和侧表面上，允许这些吸气层用作捕获位置以抵抗金属污染，在组装过程中后侧研磨后产生。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式