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1. 发明授权

US06366129B1 Method and apparatus for buffering an input-output node of an integrated circuit 有权
标题翻译：用于缓冲集成电路的输入 - 输出节点的方法和装置
公开(公告)号：US06366129B1
公开(公告)日：2002-04-02
申请号：US09189341
申请日：1998-11-10
申请人： Kenneth R. Douglas, III , Harry Muljono , Stefan Rusu
发明人： Kenneth R. Douglas, III , Harry Muljono , Stefan Rusu
IPC分类号： H03K300
CPC分类号： H03K19/0005 , H03K19/00361
摘要： An input-output (I-O) buffer for an integrated circuit. The buffer includes a controller and first and second groups of transistors to pull the node up and down, respectively. The controller is configured to turn on a transistor from the first group to drive a high bit on the node during a first period of time. The controller is further configured to turn on transistors from both the first and second groups, simultaneously, to terminate the node during a second period of time.
摘要翻译：用于集成电路的输入输出（I-O）缓冲器。缓冲器包括一个控制器以及分别将节点上下拉动的第一和第二组晶体管。控制器被配置为在第一时间段期间从第一组导通晶体管以驱动节点上的高位。控制器还被配置为同时从第一组和第二组两者接通晶体管，以在第二时间段期间终止节点。

2. 发明授权

US06311285B1 Method and apparatus for source synchronous transfers at frequencies including an odd fraction of a core frequency 有权
$Method and apparatus for source synchronous transfers at frequencies including an odd fraction of a core frequency$
标题翻译：用于在包括核心频率的奇数分数的频率处进行源同步传输的方法和装置
公开(公告)号：US06311285B1
公开(公告)日：2001-10-30
申请号：US09300538
申请日：1999-04-27
申请人： Pablo M. Rodriguez , Kenneth R. Douglas , Alper Llkbahar , Harry Muljono
发明人： Pablo M. Rodriguez , Kenneth R. Douglas , Alper Llkbahar , Harry Muljono
IPC分类号： G06F104
CPC分类号： G06F13/4217
摘要： A method and apparatus for source synchronous transfers at frequencies including an odd fraction of a core frequency. A disclosed apparatus includes a signal driver circuit and a strobe signal driver circuit. The signal driver circuit is coupled to generate a cycle for a first signal at a first frequency from a core signal from a core operating at a core clock frequency that is an odd fractional multiple of the first frequency. The strobe signal driver circuit is coupled to generate a strobe signal at an intermediate point of the cycle to allow latching of the first signal triggered by the strobe signal.
摘要翻译：用于在包括核心频率的奇数分数的频率处进行源同步传输的方法和装置。所公开的设备包括信号驱动器电路和选通信号驱动器电路。信号驱动器电路被耦合以从核心时钟频率处的核心信号以第一频率产生第一信号的周期，核心时钟频率是第一频率的奇数分数倍。选通信号驱动器电路被耦合以在周期的中间点产生选通信号，以允许锁存由选通信号触发的第一信号。

3. 发明授权

US06232814B1 Method and apparatus for controlling impedance on an input-output node of an integrated circuit 有权
标题翻译：用于控制集成电路的输入 - 输出节点上的阻抗的方法和装置
公开(公告)号：US06232814B1
公开(公告)日：2001-05-15
申请号：US09189541
申请日：1998-11-10
申请人： Kenneth R. Douglas, III
发明人： Kenneth R. Douglas, III
IPC分类号： H03H1126
CPC分类号： H03K19/0005
摘要： An input-output (I-O) buffer for an I-O node of an integrated circuit. The buffer includes a group of transistors to pull the node up. A shift register has each of two or more of its storage cells coupled to a gate of each of the transistors to control the impedance of the buffer.
摘要翻译：用于集成电路的I-O节点的输入输出（I-O）缓冲器。缓冲器包括一组用于将节点向上拉的晶体管。移位寄存器具有耦合到每个晶体管的栅极的两个或多个存储单元中的每一个以控制缓冲器的阻抗。

4. 发明授权

US5381059A CMOS tristateable buffer 失效
标题翻译： CMOS三态缓冲器
公开(公告)号：US5381059A
公开(公告)日：1995-01-10
申请号：US175643
申请日：1993-12-30
申请人： Kenneth R. Douglas
发明人： Kenneth R. Douglas
IPC分类号： H03K19/003 , H03K19/0185 , H03K19/094 , H03K19/00 , H03K19/0175
CPC分类号： H03K19/018585 , H03K19/00315 , H03K19/09429
摘要： A CMOS buffer for a mixed or singular voltage system includes an input stage circuit for converting input data compatible with transistor-transistor logic (TTL) levels to an internal signal compatible with CMOS logic levels. The buffer also includes an output driver circuit generating a pair of drive signals and a first pair of control signals in response to the internal signal. The output driver predriver circuitry also receives as inputs an enable signal for controlling the tristateablity of the buffer, and a mode signal for selecting between relatively fast versus slow output switching. A final stage circuit is configured to provide relatively fast switching at the output node when the mode signal is high, and relatively slow switching at the output node when the mode signal is low. A feedback circuit couples the input data signal to the output node as well as receiving the pair of drive signals from the output predriver circuit. The feedback circuit generates the second pair of control signals coupled to the final stage circuitry which prevents leakage current from flowing within the buffer whenever the buffer is in a tristate mode of operation and a relatively high voltage is applied to the output node.
摘要翻译：用于混合或奇异电压系统的CMOS缓冲器包括用于将与晶体管晶体管逻辑（TTL）电平兼容的输入数据转换为与CMOS逻辑电平兼容的内部信号的输入级电路。缓冲器还包括响应于内部信号产生一对驱动信号和第一对控制信号的输出驱动器电路。输出驱动器预驱动电路还接收用于控制缓冲器的三态的使能信号作为输入，以及用于在相对快速到慢速输出切换之间进行选择的模式信号。最后一级电路被配置为当模式信号为高时在输出节点处提供相对快速的切换，并且当模式信号为低时在输出节点处提供相对较慢的切换。反馈电路将输入数据信号耦合到输出节点，并从输出预驱动电路接收一对驱动信号。反馈电路产生耦合到最终级电路的第二对控制信号，每当缓冲器处于三态运行模式并且相对高的电压被施加到输出节点时，防止漏电流在缓冲器内流动。

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