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1. 发明申请

US20050169291A1 System and method for operating a packet buffer in an intermediate node 有权
标题翻译：用于在中间节点中操作分组缓冲器的系统和方法
公开(公告)号：US20050169291A1
公开(公告)日：2005-08-04
申请号：US11090734
申请日：2005-03-25
申请人： Kenneth Key , Kwok Mak , Xiaoming Sun
发明人： Kenneth Key , Kwok Mak , Xiaoming Sun
IPC分类号： H04L12/56 , H04L29/06 , H04L29/08 , H04L12/28
CPC分类号： H04L29/06 , H04L49/90 , H04L69/329
摘要： A technique implements a novel high-speed high-density packet buffer utilizing a combination of high-speed and low-speed memory devices. The novel packet buffer is organized as a plurality of FIFO queues where each FIFO queue is associated with a particular input or output line. Each queue comprises a high-speed cache portion that resides in high-speed memory and a low-speed high-density portion that resides in low-speed high-density memory. The high-speed cache portion contains FIFO data that contains head and/or tail associated with the novel FIFO queue. The low-speed high-density portion contains FIFO data that is not contained in the high-speed cache portion.
摘要翻译：一种技术实现了一种利用高速和低速存储器件组合的新型高速高密度分组缓冲器。新颖的分组缓冲器被组织为多个FIFO队列，其中每个FIFO队列与特定输入或输出线相关联。每个队列包括位于高速存储器中的高速缓存部分和位于低速高密度存储器中的低速高密度部分。高速缓存部分包含FIFO数据，其包含与新颖的FIFO队列相关联的头部和/或尾部。低速高密度部分包含不包含在高速缓存部分中的FIFO数据。

2. 发明申请

US20050125643A1 Architecture for a processor complex of an arrayed pipelined processing engine 有权
标题翻译：用于处理器阵列的流水线处理引擎的架构
公开(公告)号：US20050125643A1
公开(公告)日：2005-06-09
申请号：US11023283
申请日：2004-12-27
申请人： Michael Wright , Darren Kerr , Kenneth Key , William Jennings
发明人： Michael Wright , Darren Kerr , Kenneth Key , William Jennings
IPC分类号： G06F15/78 , G06F12/00
CPC分类号： G06F15/8053
摘要： A processor complex architecture facilitates accurate passing of transient data among processor complex stages of a pipelined processing engine. The processor complex comprises a central processing unit (CPU) coupled to an instruction memory and a pair of context data memory structures via a memory manager circuit. The context memories store transient “context” data for processing by the CPU in accordance with instructions stored in the instruction memory. The architecture further comprises data mover circuitry that cooperates with the context memories and memory manager to provide a technique for efficiently passing data among the stages in a manner that maintains data coherency in the processing engine. An aspect of the architecture is the ability of the CPU to operate on the transient data substantially simultaneously with the passing of that data by the data mover.
摘要翻译：处理器复杂架构有助于在流水线处理引擎的处理器复杂级之间准确地传递瞬态数据。处理器复合体包括经由存储器管理器电路耦合到指令存储器和一对上下文数据存储器结构的中央处理单元（CPU）。上下文存储器存储瞬时“上下文”数据，以便CPU根据存储在指令存储器中的指令进行处理。该架构还包括与上下文存储器和存储器管理器配合的数据移动器电路，以提供一种用于以维持处理引擎中的数据一致性的方式在各个级之间高效地传送数据的技术。该体系结构的一个方面是CPU能够在数据移动器通过该数据时同时对瞬态数据进行操作。

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