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1. 发明授权

US4447823A SOS p--n Junction device with a thick oxide wiring insulation layer 失效
标题翻译： SOS p-n具有厚度为氧化物布线绝缘层的结型装置
公开(公告)号：US4447823A
公开(公告)日：1984-05-08
申请号：US240850
申请日：1981-03-05
申请人： Kenji Maeguchi , Hiroyuki Tango
发明人： Kenji Maeguchi , Hiroyuki Tango
IPC分类号： H01L29/78 , H01L21/762 , H01L21/86 , H01L27/12 , H01L29/786 , H01L27/02 , H01L45/00
CPC分类号： H01L21/86 , H01L21/76264 , H01L27/12 , H01L21/76272 , H01L21/76281
摘要： A semiconductor device having silicon-on-sapphire structure in which a pn junction element is formed in a silicon substrate disposed on a sapphire plate. An oxide layer is formed in the surface area of the p-type region which serves to form the pn junction elements.
摘要翻译：一种具有硅蓝宝石结构的半导体器件，其中在设置在蓝宝石板上的硅衬底中形成pn结元件。在用于形成pn结元件的p型区域的表面区域中形成氧化物层。

2. 发明授权

US4395726A Semiconductor device of silicon on sapphire structure having FETs with different thickness polycrystalline silicon films 失效
标题翻译：蓝宝石结构的硅半导体器件具有不同厚度的多晶硅膜的FET
公开(公告)号：US4395726A
公开(公告)日：1983-07-26
申请号：US134678
申请日：1980-03-27
申请人： Kenji Maeguchi
发明人： Kenji Maeguchi
IPC分类号： H01L27/08 , H01L21/86 , H01L27/12 , H01L29/78 , H01L29/786 , H01L27/02
CPC分类号： H01L27/1233 , H01L21/86 , H01L27/1214
摘要： A semiconductor device has a plurality of field effect transistors on an insulating substrate. A semiconductor film constituting at least one of the plurality of field effect transistors is thinner than a semiconductor film of the other field effect transistor or transistors.
摘要翻译：半导体器件在绝缘基板上具有多个场效应晶体管。构成多个场效应晶体管中的至少一个的半导体膜比另一场效应晶体管或晶体管的半导体膜薄。

3. 发明授权

US4498224A Method of manufacturing a MOSFET using accelerated ions to form an amorphous region 失效
标题翻译：使用加速离子制造MOSFET以形成非晶区域的方法
公开(公告)号：US4498224A
公开(公告)日：1985-02-12
申请号：US544991
申请日：1982-10-24
申请人： Kenji Maeguchi
发明人： Kenji Maeguchi
IPC分类号： H01L21/225 , H01L21/265 , H01L21/336 , H01L27/12 , H01L29/08 , H01L29/78 , H01L29/786 , H01L21/425
CPC分类号： H01L29/0847 , H01L21/2253 , H01L21/26506 , H01L21/26513 , H01L29/78621 , Y10S148/082
摘要： A method for manufacturing MOSFET type semiconductor devices comprises forming a gate insulation layer and a gate electrode on a single crystal semiconductor substrate; introducing impurities in the substrate using the gate electrode as a mask; introducing accelerated ions deeper into the substrate than the impurities and overlapping at least a portion of the region in which the impurities are introduced in order to convert that portion to an amorphous state; diffusing the impurities into the amorphous region using a heating atmosphere, in order to form source and drain regions and, at the same time, converting the amorphous region to a single crystal; and forming source and drain electrodes in contact with the source and drain regions.
摘要翻译：一种用于制造MOSFET型半导体器件的方法，包括在单晶半导体衬底上形成栅极绝缘层和栅电极; 使用栅电极作为掩模在基板中引入杂质; 将加速离子比杂质更深地引入衬底中，并且与引入杂质的区域的至少一部分重叠以将该部分转化为非晶状态; 使用加热气氛将杂质扩散到非晶区域，以形成源区和漏区，同时将非晶区转化为单晶; 以及形成与源极和漏极区域接触的源极和漏极电极。

4. 发明授权

US5061983A Semiconductor device having a metal silicide layer connecting two semiconductors 失效
标题翻译：具有连接两个半导体的金属硅化物层的半导体器件
公开(公告)号：US5061983A
公开(公告)日：1991-10-29
申请号：US318411
申请日：1989-02-28
申请人： Hideharu Egawa , Yoshio Nishi , Kenji Maeguchi
发明人： Hideharu Egawa , Yoshio Nishi , Kenji Maeguchi
IPC分类号： H01L21/768 , H01L21/28 , H01L23/532 , H01L27/12 , H01L29/43
CPC分类号： H01L23/53271 , H01L27/12 , H01L2924/0002
摘要： A method for manufacturing a semiconductor device that includes p- and n-type regions formed on an insulating substrate, and an interconnection layer electrically coupled with these p- and n-type regions. The interconnection layer is an n-type polycrystalline silicon layer which is electrically coupled with the p- and n-type regions through a metal silicide film formed between the interconnection layer and the p- and n-type regions.
摘要翻译：一种制造半导体器件的方法，该半导体器件包括形成在绝缘衬底上的p型和n型区域，以及与这些p型和n型区域电耦合的互连层。互连层是通过在互连层和p型区域和n型区域之间形成的金属硅化物膜与p型区域和n型区域电耦合的n型多晶硅层。

5. 发明授权

US4619037A Method of manufacturing a semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US4619037A
公开(公告)日：1986-10-28
申请号：US798728
申请日：1985-11-19
申请人： Shinji Taguchi , Homare Matsumura , Kenji Maeguchi
发明人： Shinji Taguchi , Homare Matsumura , Kenji Maeguchi
IPC分类号： H01L23/522 , H01L21/302 , H01L21/3065 , H01L21/768 , H01L21/44
CPC分类号： H01L21/76877
摘要： A method of manufacturing a semiconductor device is disclosed. In the manufacturing method, an impurity diffusion layer as a first interconnection layer is formed on a semiconductor substrate. Then, an aluminum layer as a second interconnection layer is formed on the semiconductor substrate with an insulating film interposing therebetween. Another insulating layer is further formed on the aluminum layer. An anisotropic etching process is applied to the insulating layer, the second interconnection layer, and the insulating film, thereby forming a contact extending up to the first interconnection layer through these layers, and the insulating film. After the formation of the contact hole, an aluminum layer is formed on the entire surface of the insulating film including the inner surface of the contact hole. The aluminum layer formed in the contact hole electrically interconnects the first and second interconnecting layers.
摘要翻译：公开了制造半导体器件的方法。在制造方法中，在半导体衬底上形成作为第一互连层的杂质扩散层。然后，在半导体衬底上形成作为第二互连层的铝层，其间插入有绝缘膜。在铝层上进一步形成另一绝缘层。对绝缘层，第二互连层和绝缘膜施加各向异性蚀刻工艺，由此形成通过这些层延伸到第一互连层的接触和绝缘膜。在形成接触孔之后，在包括接触孔的内表面的绝缘膜的整个表面上形成铝层。形成在接触孔中的铝层电连接第一和第二互连层。

6. 发明授权

US4564583A Method for manufacturing a semiconductor device 失效
标题翻译：半导体器件的制造方法
公开(公告)号：US4564583A
公开(公告)日：1986-01-14
申请号：US575921
申请日：1984-02-01
申请人： Kenji Maeguchi
发明人： Kenji Maeguchi
IPC分类号： G03F7/095 , H01L21/027 , H01L21/265 , H01L21/266 , H01L21/762 , H01L21/8238 , H01L27/092 , G03C5/00 , H01L21/00
CPC分类号： G03F7/095 , H01L21/0271 , H01L21/0274 , H01L21/2652 , H01L21/266 , H01L21/76218 , H01L21/823807 , H01L27/0928
摘要： Disclosed is a method for manufacturing a semiconductor device which comprises a process for forming a positive-type resist film and a negative-type resist film on a semiconductor substrate, a process for exposing predetermined regions of both resist films to radiation, a process for developing the upper resist film to form a first resist pattern adapted to be used as a mask for ion-implantation, a process for developing the lower resist film to form a second resist pattern opposite to the first resist pattern after peeling off the first resist pattern, and a process for treatment the semiconductor substrate using the second resist pattern as a mask.
摘要翻译：公开了一种半导体器件的制造方法，其包括在半导体衬底上形成正型抗蚀剂膜和负型抗蚀剂膜的工艺，用于将两个抗蚀剂膜的预定区域暴露于辐射的工艺，用于显影的工艺形成适于用作离子注入掩模的第一抗蚀剂图案的上抗蚀剂膜，在剥离第一抗蚀剂图案之后，形成与第一抗蚀剂图案相对的第二抗蚀剂图案的下部抗蚀剂膜的工艺，以及使用第二抗蚀剂图案作为掩模来处理半导体衬底的工艺。

7. 发明授权

US4491856A Semiconductor device having contacting but electrically isolated semiconductor region and interconnection layer of differing conductivity types 失效
标题翻译：具有接触但电隔离的半导体区域和不同导电类型的互连层的半导体器件
公开(公告)号：US4491856A
公开(公告)日：1985-01-01
申请号：US582864
申请日：1984-02-27
申请人： Hideharu Egawa , Yoshio Nishi , Kenji Maeguchi
发明人： Hideharu Egawa , Yoshio Nishi , Kenji Maeguchi
IPC分类号： H01L23/52 , H01L21/3205 , H01L23/522 , H01L23/532 , H01L27/12 , H01L23/48 , H01L27/02 , H01L29/78
CPC分类号： H01L27/12 , H01L23/522 , H01L23/53271 , H01L2924/0002
摘要： A semiconductor device includes p- and n-type semiconductor layers formed on an insulating substrate and an n-type interconnection layer formed to be electrically coupled with said n-type semiconductor layer. The n-type interconnection layer is formed in contact with the p-type semiconductor layer and is set at such a potential as to apply a reverse voltage across the p-n junction between the n-type interconnection layer and p-type semiconductor layer, so as to electrically isolate the n-type interconnection layer from the p-type semiconductor layer.
摘要翻译：半导体器件包括形成在绝缘基板上的p型和n型半导体层以及形成为与所述n型半导体层电耦合的n型互连层。 n型互连层形成为与p型半导体层接触，并且被设置为在n型互连层和p型半导体层之间的pn结上施加反向电压的电位，从而以将n型互连层与p型半导体层电隔离。

8. 发明授权

US4463492A Method of forming a semiconductor device on insulating substrate by selective amorphosization followed by simultaneous activation and reconversion to single crystal state 失效
标题翻译：通过选择性的放电形成半导体器件在绝缘衬底上形成半导体器件的方法，然后同时激活并重新转化为单晶态
公开(公告)号：US4463492A
公开(公告)日：1984-08-07
申请号：US423146
申请日：1982-09-24
申请人： Kenji Maeguchi
发明人： Kenji Maeguchi
IPC分类号： H01L27/00 , H01L21/20 , H01L21/265 , H01L21/324 , H01L21/86 , H01L29/78 , H01L29/786 , H01L21/263 , H01L21/225
CPC分类号： H01L21/324 , H01L21/0242 , H01L21/02532 , H01L21/02587 , H01L21/02667 , H01L21/02694 , H01L21/26506 , H01L21/2652 , Y10S148/091 , Y10S148/093
摘要： A method for manufacturing a semiconductor device of a type in which a semiconductor element is formed on an insulating substrate. After ions which break the regularity of the crystal lattice of a monocrystalline semiconductor layer formed on the insulating substrate are implanted to form an amorphous semiconductor layer in part of the monocrystalline semiconductor layer, and after an impurity is doped in the semiconductor layer, a single annealing process is performed to recrystallize the amorphous semiconductor layer and at the same time to activate the doped impurity.
摘要翻译：一种半导体器件的制造方法，其中半导体器件形成在绝缘衬底上。在绝缘基板上形成的单晶半导体层的晶格的规则性的离子被注入，在单晶半导体层的一部分中形成非晶半导体层，在半导体层中杂质掺杂后，进行处理以使非晶半导体层重结晶，同时激活掺杂杂质。

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