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1. 发明申请

US20070003161A1 Computation transformations for streaming applications on multiprocessors 有权
标题翻译：多处理器上的流应用的计算转换
公开(公告)号：US20070003161A1
公开(公告)日：2007-01-04
申请号：US11170978
申请日：2005-06-30
申请人： Shih-wei Liao , Zhaohui Du , Gansha Wu , Ken Lueh , Zhiwei Ying , Jinzhan Peng
发明人： Shih-wei Liao , Zhaohui Du , Gansha Wu , Ken Lueh , Zhiwei Ying , Jinzhan Peng
IPC分类号： G06K9/36
CPC分类号： G06F8/456
摘要： A method including providing a stream of content to a processor, transforming kernels within the stream of content through affine modeling, transforming the affine modeled kernels, stream contracting kernel processes, and stream blocking the kernel processes.
摘要翻译：一种方法，包括向处理器提供内容流，通过仿射建模，改变仿射建模的内核，流收缩内核进程和流封锁内核进程来转换内容流内的内核。

2. 发明申请

US20130297919A1 EFFICIENT IMPLEMENTATION OF RSA USING GPU/CPU ARCHITECTURE 有权
标题翻译：使用GPU / CPU架构的RSA的有效实现
公开(公告)号：US20130297919A1
公开(公告)日：2013-11-07
申请号：US13997239
申请日：2011-11-30
申请人： Xiaozhu Kang , Biju George , Ken Lueh
发明人： Xiaozhu Kang , Biju George , Ken Lueh
IPC分类号： G06F9/38
CPC分类号： G06F9/38 , G06F8/452 , G06F9/30 , G06F21/00
摘要： Various embodiments are directed to a heterogeneous processor architecture comprised of a CPU and a GPU on the same processor die. The heterogeneous processor architecture may optimize source code in a GPU compiler using vector strip mining to reduce instructions of arbitrary vector lengths into GPU supported vector lengths and loop peeling. It may be first determined that the source code is eligible for optimization if more than one machine code instruction of compiled source code under-utilizes GPU instruction bandwidth limitations. The initial vector strip mining results may be discarded and the first iteration of the inner loop body may be peeled out of the loop. The type of operands in the source code may be lowered and the peeled out inner loop body of source code may be vector strip mined again to obtain optimized source code.
摘要翻译：各种实施例涉及由同一处理器管芯上的CPU和GPU组成的异构处理器架构。异构处理器架构可以使用向量带挖掘来优化GPU编译器中的源代码，以将任意矢量长度的指令减少到GPU支持的矢量长度和循环剥离。如果编译源代码的多个机器码指令利用了GPU指令带宽限制，则可以首先确定源代码是否符合优化条件。可以丢弃初始矢量条带挖掘结果，并且内环体的第一次迭代可能被剥离出环路。可以降低源代码中的操作数类型，并且可以再次剥离源代码的剥离内圈体，以获得优化的源代码。

3. 发明授权

US07953158B2 Computation transformations for streaming applications on multiprocessors 有权
标题翻译：多处理器上的流应用的计算转换
公开(公告)号：US07953158B2
公开(公告)日：2011-05-31
申请号：US11170978
申请日：2005-06-30
申请人： Shih-wei Liao , Zhaohui Du , Gansha Wu , Ken Lueh , Zhiwei Ying , Jinzhan Peng
发明人： Shih-wei Liao , Zhaohui Du , Gansha Wu , Ken Lueh , Zhiwei Ying , Jinzhan Peng
IPC分类号： H04N7/18
CPC分类号： G06F8/456
摘要： A method including providing a stream of content to a processor, transforming kernels within the stream of content through affine modeling, transforming the affine modeled kernels, stream contracting kernel processes, and stream blocking the kernel processes.
摘要翻译：一种方法，包括向处理器提供内容流，通过仿射建模，改变仿射建模的内核，流收缩内核进程和流封锁内核进程来转换内容流内的内核。

4. 发明申请

US20060288338A1 Offset threaded code 审中-公开
标题翻译：偏移线程代码
公开(公告)号：US20060288338A1
公开(公告)日：2006-12-21
申请号：US11154077
申请日：2005-06-15
申请人： Jinzhan Peng , Ken Lueh , Gansha Wu
发明人： Jinzhan Peng , Ken Lueh , Gansha Wu
IPC分类号： G06F9/45
CPC分类号： G06F9/45508 , G06F9/45504
摘要： Translating a virtual machine instruction into a value which when logically combined with a base value yields an address of interpretation code to perform the virtual machine instruction.
摘要翻译：将虚拟机指令转换成与基础值逻辑组合时产生一个解释代码的地址以执行虚拟机指令的值。

5. 发明授权

US09262166B2 Efficient implementation of RSA using GPU/CPU architecture 有权
标题翻译：使用GPU / CPU架构高效实现RSA
公开(公告)号：US09262166B2
公开(公告)日：2016-02-16
申请号：US13997239
申请日：2011-11-30
申请人： Xiaozhu Kang , Biju George , Ken Lueh
发明人： Xiaozhu Kang , Biju George , Ken Lueh
IPC分类号： G06F9/45 , G06F9/38 , G06F9/30 , G06F21/00
CPC分类号： G06F9/38 , G06F8/452 , G06F9/30 , G06F21/00
摘要： Various embodiments are directed to a heterogeneous processor architecture comprised of a CPU and a GPU on the same processor die. The heterogeneous processor architecture may optimize source code in a GPU compiler using vector strip mining to reduce instructions of arbitrary vector lengths into GPU supported vector lengths and loop peeling. It may be first determined that the source code is eligible for optimization if more than one machine code instruction of compiled source code under-utilizes GPU instruction bandwidth limitations. The initial vector strip mining results may be discarded and the first iteration of the inner loop body may be peeled out of the loop. The type of operands in the source code may be lowered and the peeled out inner loop body of source code may be vector strip mined again to obtain optimized source code.
摘要翻译：各种实施例涉及由同一处理器管芯上的CPU和GPU组成的异构处理器架构。异构处理器架构可以使用向量带挖掘来优化GPU编译器中的源代码，以将任意矢量长度的指令减少到GPU支持的矢量长度和循环剥离。如果编译源代码的多个机器码指令利用了GPU指令带宽限制，则可以首先确定源代码是否符合优化条件。可以丢弃初始矢量条带挖掘结果，并且内环体的第一次迭代可能被剥离出环路。可以降低源代码中的操作数类型，并且可以再次剥离源代码的剥离内圈体，以获得优化的源代码。

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