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    • 1. 发明授权
    • Systems, methods and computer program products for prediction of
defect-related failures in integrated circuits
    • 用于预测集成电路中缺陷相关故障的系统,方法和计算机程序产品
    • US5822218A
    • 1998-10-13
    • US703518
    • 1996-08-27
    • Mohamed S. MoosaKelvin F. Poole
    • Mohamed S. MoosaKelvin F. Poole
    • G01R31/3183G06F17/50
    • G01R31/31835
    • Systems, methods and computer program products for predicting defect-related failures in integrated circuits produced by an integrated circuit fabrication process identify objects in a circuit layout for the integrated circuit design, each object having a location in the circuit layout and a reliability connectivity in the integrated circuit design. Sample object defects are generated for the identified objects, each sample object defect representing a defect produced in an object by the integrated circuit fabrication process and having a defect magnitude associated therewith. An accelerated life defect influence model is identified for each sample object defect, relating the lifetime of an object to the defect magnitude of a defect in the object. Sample object lifetimes are generated from the defect magnitudes associated with the sample object defects according to the corresponding identified accelerated life defect influence models. A prediction of the reliability of integrated circuits is generated from the sample object lifetimes according to the reliability connectivity of the associated objects in the integrated circuit design. Preferably, the accelerated life defect influence models include log-linear regression models, which may include deterministic object lifetime functions, each relating the defect magnitude of the at least one sample object defect to one object lifetime value, and log-linear object lifetime distributions, each relating the defect magnitude of a sample object defect to a plurality of object lifetime values.
    • 用于预测由集成电路制造过程产生的集成电路中的缺陷相关故障的系统,方法和计算机程序产品识别用于集成电路设计的电路布局中的对象,每个对象在电路布局中具有位置,并且在 集成电路设计。 针对所识别的对象产生样本对象缺陷,每个样本对象缺陷表示通过集成电路制造工艺在对象中产生的缺陷并且具有与其相关联的缺陷量级。 针对每个样本对象缺陷,识别加速生命缺陷影响模型,将对象的生命周期与对象缺陷的缺陷大小相关联。 根据相应的识别的加速寿命缺陷影响模型,从与样本对象缺陷相关的缺陷量产生样本对象的生命周期。 根据集成电路设计中的相关对象的可靠性连接性,从采样对象的寿命产生集成电路的可靠性的预测。 优选地,加速寿命缺陷影响模型包括对数线性回归模型,其可以包括确定性对象寿命函数,每个函数将至少一个样本对象缺陷的缺陷大小与一个对象寿命值相关联,以及对数线性对象寿命分布, 每个将样本对象缺陷的缺陷大小与多个对象寿命值相关联。
    • 2. 发明授权
    • Process for forming layers on substrates
    • 在基板上形成层的工艺
    • US06569249B1
    • 2003-05-27
    • US09551385
    • 2000-04-18
    • Rajendra SinghKelvin F. Poole
    • Rajendra SinghKelvin F. Poole
    • B05B500
    • H01L21/6715H01L21/02381H01L21/02521H01L21/0262H01L21/02628H01L21/288H01L21/67115H01L31/1804Y02E10/547Y02P70/521
    • The present invention is generally directed to various processes and systems for forming layers and coatings on substrates, such as semiconductor wafers and solar cells. In one embodiment, the process of the present invention is directed to forming a layer on a substrate from a liquid precursor. The liquid precursor is atomized and exposed to light energy. Besides light energy, the parent material may also be exposed to an electric field and/or to sonic energy. In an alternative embodiment of the present invention a stress measurement device monitors stress in the substrate as a layer is deposited on the substrate. This stress measurement information is then sent to a controller for automatically controlling the amount of energy, such as light energy being emitted onto the substrate.
    • 本发明一般涉及用于在诸如半导体晶片和太阳能电池的衬底上形成层和涂层的各种工艺和系统。 在一个实施方案中,本发明的方法涉及从液体前体在基材上形成层。 液体前体被雾化并暴露于光能。 除了光能之外,母材还可能暴露于电场和/或声波能量。 在本发明的替代实施例中,当层沉积在衬底上时,应力测量装置监测衬底中的应力。 然后将该应力测量信息发送到控制器,以自动控制能量的量,例如发射到衬底上的光能。