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1. 发明申请

US20120191900A1 MEMORY MANAGEMENT DEVICE 审中-公开
标题翻译：内存管理设备
公开(公告)号：US20120191900A1
公开(公告)日：2012-07-26
申请号：US13351582
申请日：2012-01-17
申请人： Atsushi KUNIMATSU , Masaki MIYAGAWA , Hiroshi NOZUE , Kazuhiro KAWAGOME , Hiroto NAKAI , Hiroyuki SAKAMOTO , Tsutomu OWA , Tsutomu UNESAKI , Reina NISHINO , Kenichi MAEDA , Mari TAKADA
发明人： Atsushi KUNIMATSU , Masaki MIYAGAWA , Hiroshi NOZUE , Kazuhiro KAWAGOME , Hiroto NAKAI , Hiroyuki SAKAMOTO , Tsutomu OWA , Tsutomu UNESAKI , Reina NISHINO , Kenichi MAEDA , Mari TAKADA
IPC分类号： G06F12/02
CPC分类号： G06F3/0604 , G06F3/061 , G06F3/0631 , G06F3/0638 , G06F3/0653 , G06F3/0679 , G06F12/0223 , G06F12/0246 , G06F12/06 , G06F2212/1016 , G06F2212/1036 , G06F2212/205 , G06F2212/7201 , G06F2212/7202 , G06F2212/7208
摘要： A memory management device of an example of the invention controls writing into and reading from a main memory including a nonvolatile semiconductor memory and a volatile semiconductor memory in response to a writing request and a reading request from a processor. The memory management device includes a coloring information storage unit that stores coloring information generated based on a data characteristic of write target data to be written into at least one of the nonvolatile semiconductor memory and the volatile semiconductor memory, and a writing management unit that references the coloring information to determines a region into which the write target data is written from the nonvolatile semiconductor memory and the volatile semiconductor memory.
摘要翻译：本发明实施例的存储器管理装置响应于来自处理器的写入请求和读取请求，控制对包括非易失性半导体存储器和易失性半导体存储器的主存储器的写入和读取。存储器管理装置包括着色信息存储单元，该着色信息存储单元存储基于要写入到非易失性半导体存储器和易失性半导体存储器中的至少一个的写入目标数据的数据特性而生成的着色信息;以及写入管理单元，着色信息以确定从非易失性半导体存储器和易失性半导体存储器写入写目标数据的区域。

2. 发明申请

US20100064111A1 INFORMATION PROCESSING DEVICE INCLUDING MEMORY MANAGEMENT DEVICE MANAGING ACCESS FROM PROCESSOR TO MEMORY AND MEMORY MANAGEMENT METHOD 有权
标题翻译：信息处理设备，包括存储器管理设备管理从处理器访问存储器和存储器管理方法
公开(公告)号：US20100064111A1
公开(公告)日：2010-03-11
申请号：US12555952
申请日：2009-09-09
申请人： Atsushi Kunimatsu , Hiroto Nakai , Hiroyuki Sakamoto , Kenichi Maeda , Masaki Miyagawa , Hiroshi Nozue , Kazuhiro Kawagome
发明人： Atsushi Kunimatsu , Hiroto Nakai , Hiroyuki Sakamoto , Kenichi Maeda , Masaki Miyagawa , Hiroshi Nozue , Kazuhiro Kawagome
IPC分类号： G06F12/00 , G06F12/16 , G06F12/02
CPC分类号： G06F12/0804 , G06F12/0246 , G06F12/08 , G06F12/0888 , G06F2212/1036 , G06F2212/2022 , G06F2212/205 , G06F2212/7201
摘要： A device according to an example of the invention comprises a section which accepts a write destination logical address and write target data from a processor, the write destination logical address indicating a write position to write the write target data into a composite memory which includes a first memory and a nonvolatile second memory, a section which determines a write destination physical address corresponding to the write destination logical address so that the number of times of access to the second memory is smaller than the number of times of access to the first memory, a section which stores, in a storage section, address conversion data associating the write destination logical address with the write destination physical address, and a section which writes the write target data into a position in the composite memory indicated by the write destination physical address.
摘要翻译：根据本发明的示例的设备包括接收来自处理器的写入目的地逻辑地址和写入目标数据的部分，写入目的地逻辑地址指示写入位置以将写入目标数据写入复合存储器，该复合存储器包括第一存储器和非易失性第二存储器，确定与写入目的地逻辑地址相对应的写目的物理地址的部分，使得对第二存储器的访问次数小于对第一存储器的访问次数，在存储部中存储将写入目的地逻辑地址与写入目的地物理地址相关联的地址转换数据以及将写入目标数据写入由写入目的地物理地址指示的复合存储器中的位置的部分。

3. 发明申请

US20090271785A1 INFORMATION PROCESSING APPARATUS AND CONTROL METHOD 审中-公开
标题翻译：信息处理装置和控制方法
公开(公告)号：US20090271785A1
公开(公告)日：2009-10-29
申请号：US12358064
申请日：2009-01-22
申请人： Kazuhiro Kawagome , Hiroshi Nakajima
发明人： Kazuhiro Kawagome , Hiroshi Nakajima
IPC分类号： G06F9/455
CPC分类号： G06F9/45533 , G06F9/4401
摘要： According to one embodiment, an information processing apparatus capable of controlling a plurality of operating systems, includes an activation module which activates an activation program, a management module which manages the plurality of operating systems to be activated by the activation module, a storage module which stores a main operating system that runs on the management module and a guest operating system that runs on the management module via a virtual activation program, and a notification module which, if a monitoring program that runs on the main operating system activated determines that a configuration of the information processing apparatus has changed, causes a notification program running on the main operating system to notify the guest operating system activated from the storage module via the virtual activation program of change information of the configuration of the information processing apparatus.
摘要翻译：根据一个实施例，能够控制多个操作系统的信息处理装置包括激活激活程序的激活模块，管理由激活模块激活的多个操作系统的管理模块;存储模块，存储在管理模块上运行的主操作系统和通过虚拟激活程序在管理模块上运行的客户操作系统，以及通知模块，如果在主操作系统上运行的监视程序被激活，则确定配置信息处理装置的变更信息，使得主操作系统上运行的通知程序经由信息处理装置的结构的变更信息的虚拟激活程序通知从存储模块启动的客人操作系统。

4. 发明授权

US09280466B2 Information processing device including memory management device managing access from processor to memory and memory management method 有权
标题翻译：信息处理装置，包括管理从处理器到存储器的访问的存储器管理装置和存储器管理方法
公开(公告)号：US09280466B2
公开(公告)日：2016-03-08
申请号：US12555952
申请日：2009-09-09
申请人： Atsushi Kunimatsu , Hiroto Nakai , Hiroyuki Sakamoto , Kenichi Maeda , Masaki Miyagawa , Hiroshi Nozue , Kazuhiro Kawagome
发明人： Atsushi Kunimatsu , Hiroto Nakai , Hiroyuki Sakamoto , Kenichi Maeda , Masaki Miyagawa , Hiroshi Nozue , Kazuhiro Kawagome
IPC分类号： G06F12/08 , G06F12/02
CPC分类号： G06F12/0804 , G06F12/0246 , G06F12/08 , G06F12/0888 , G06F2212/1036 , G06F2212/2022 , G06F2212/205 , G06F2212/7201
摘要： A device according to an example of the invention comprises a section which accepts a write destination logical address and write target data from a processor, the write destination logical address indicating a write position to write the write target data into a composite memory which includes a first memory and a nonvolatile second memory, a section which determines a write destination physical address corresponding to the write destination logical address so that the number of times of access to the second memory is smaller than the number of times of access to the first memory, a section which stores, in a storage section, address conversion data associating the write destination logical address with the write destination physical address, and a section which writes the write target data into a position in the composite memory indicated by the write destination physical address.
摘要翻译：根据本发明的示例的设备包括接收来自处理器的写入目的地逻辑地址和写入目标数据的部分，写入目的地逻辑地址指示写入位置以将写入目标数据写入复合存储器，该复合存储器包括第一存储器和非易失性第二存储器，确定与写入目的地逻辑地址相对应的写目的物理地址的部分，使得对第二存储器的访问次数小于对第一存储器的访问次数，在存储部中存储将写入目的地逻辑地址与写入目的地物理地址相关联的地址转换数据以及将写入目标数据写入由写入目的地物理地址指示的复合存储器中的位置的部分。

5. 发明申请

US20110246600A1 MEMORY SHARING APPARATUS 审中-公开
标题翻译：记忆共享装置
公开(公告)号：US20110246600A1
公开(公告)日：2011-10-06
申请号：US13077021
申请日：2011-03-31
申请人： Yoshiteru KAGEYAMA , Kazuhiro Kawagome , Tetsuo Hasegawa
发明人： Yoshiteru KAGEYAMA , Kazuhiro Kawagome , Tetsuo Hasegawa
IPC分类号： G06F15/167
CPC分类号： G06F15/17331 , G06F9/544 , H04L69/161
摘要： A memory sharing apparatus includes a server, a host and a client. The server includes a shared page which is an entity of a shared memory, a share setting page which is data in which an index value of each shared page is collected, and a grant table in which a page frame number of each share setting page and the index value are stored so as to correspond to each other. The host includes a database in which the index value in the grant table is managed. The client includes the shared page and a shared page area to which the shared page is mapped, and a share setting page area to which the share setting page is mapped.
摘要翻译：存储器共享装置包括服务器，主机和客户机。服务器包括作为共享存储器的实体的共享页面，作为收集每个共享页面的索引值的数据的共享设置页面，以及每个共享设置页面的页面帧号和索引值被存储以便彼此对应。主机包括一个数据库，在该数据库中管理授权表中的索引值。客户端包括共享页面和共享页面映射到的共享页面区域，以及共享设置页面映射到的共享设置页面区域。

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