专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20110064984A1 SOLAR BATTERY MODULE SUBSTRATE AND SOLAR BATTERY MODULE 审中-公开
标题翻译：太阳能电池模块基板和太阳能电池模块
公开(公告)号：US20110064984A1
公开(公告)日：2011-03-17
申请号：US12882386
申请日：2010-09-15
申请人： Kazuaki TATSUMI , Kohji MIYATA , Hiroyuki NAKANISHI , Masahiro OKITA , Masato YOKOBAYASHI
发明人： Kazuaki TATSUMI , Kohji MIYATA , Hiroyuki NAKANISHI , Masahiro OKITA , Masato YOKOBAYASHI
IPC分类号： H01M6/30
CPC分类号： H01L31/0516 , H01L31/02013 , Y02E10/50
摘要： A solar battery module substrate includes an insulating substrate on which a conductive pattern and an insulating protective film are formed, the conductive pattern including: cathode mounting terminals each of which is to be connected with a cathode of a solar battery cell; anode mounting terminals each of which is to be connected with an anode of the solar battery cell; and first module wiring, the first module wiring connecting a cathode mounting terminal to be connected with a cathode of one solar battery cell with an anode mounting terminal to be connected with an anode of another solar battery cell connected in series with said one solar battery cell, the insulating protective film having at least one opening for exposing the cathode mounting terminal and the anode mounting terminal, and the opening being positioned inside a portion of the solar battery module substrate on which portion the solar battery cell is to be projected.
摘要翻译：太阳能电池模块基板包括绝缘基板，其上形成有导电图案和绝缘保护膜，所述导电图案包括：阴极安装端子，每个阴极安装端子将与太阳能电池单元的阴极连接; 每个阳极安装端子将与太阳能电池单元的阳极连接; 和第一模块布线，第一模块布线将要与一个太阳能电池单元的阴极连接的阴极安装端子与具有与所述一个太阳能电池单元串联连接的另一个太阳能电池单元的阳极连接的阳极安装端子连接所述绝缘保护膜具有至少一个开口，用于暴露所述阴极安装端子和所述阳极安装端子，并且所述开口位于所述太阳能电池模块基板的将要投射所述太阳能电池单元的部分的一部分的内部。

2. 发明申请

US20110042828A1 WIRING BOARD, SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE 有权
标题翻译：接线板，半导体器件及制造半导体器件的方法
公开(公告)号：US20110042828A1
公开(公告)日：2011-02-24
申请号：US12988697
申请日：2009-03-16
申请人： Yoshiki Sota , Kazuaki Tatsumi
发明人： Yoshiki Sota , Kazuaki Tatsumi
IPC分类号： H01L23/48 , H01L21/56
CPC分类号： H01L23/49838 , H01L23/13 , H01L23/564 , H01L24/45 , H01L24/48 , H01L24/73 , H01L2224/32225 , H01L2224/45015 , H01L2224/451 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48227 , H01L2224/48228 , H01L2224/73265 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/01322 , H01L2924/12041 , H01L2924/15151 , H01L2924/15311 , H01L2924/181 , H05K3/305 , H05K3/3452 , H05K2201/09072 , H05K2201/09772 , H05K2201/0989 , H05K2203/1178 , Y02P70/613 , H01L2924/00014 , H01L2924/00 , H01L2924/00012 , H01L2924/20752 , H01L2924/20753 , H01L2924/00015
摘要： A wiring board (10) of the present invention includes: a through hole (11b), provided in a semiconductor chip mounted region (15), penetrating the wiring board (10); and a groove pattern (13), provided on a solder resist (9) formed on the semiconductor chip mounted region (15), leading to the through hole (11b). The foregoing configuration makes it possible to guide, via the groove pattern (13) to the through hole (11b), moisture that collects in the semiconductor chip mounted region (15) and therefore to effectively discharge the moisture from the semiconductor chip mounted region (15). Thus, a semiconductor device (30) that employs the wiring board (10) does not suffer from vaporization and expansion, inside of it, due to heat that is applied at the time of manufacturing the semiconductor device (30) and at the time of mounting the semiconductor device (30) on a mount substrate. It is therefore possible to reduce expansion of the semiconductor device.
摘要翻译：本发明的布线基板（10）具备：贯通所述布线基板（10）的贯通孔（11b），设置在半导体芯片安装区域（15）中。以及设置在形成在半导体芯片安装区域（15）上的阻焊剂（9）上的通向通孔（11b）的凹槽图案（13）。上述构造使得可以经由凹槽图案（13）引导到通孔（11b），其收集在半导体芯片安装区域（15）中的湿气，并且因此有效地从半导体芯片安装区域排出水分（ 15）。因此，采用该布线基板（10）的半导体装置（30）在制造半导体装置（30）时由于加热而在其内部不会发生汽化膨胀，将半导体器件（30）安装在安装基板上。因此可以减少半导体器件的膨胀。

3. 发明申请

US20090184413A1 INSULATIVE WIRING BOARD, SEMICONDUCTOR PACKAGE USING THE SAME, AND METHOD FOR PRODUCING THE INSULATIVE WIRING BOARD 审中-公开
标题翻译：绝缘导线板，使用其的半导体封装以及用于制造绝缘导线板的方法
公开(公告)号：US20090184413A1
公开(公告)日：2009-07-23
申请号：US12212089
申请日：2008-09-17
申请人： Kazuaki TATSUMI , Yoshiki SOTA
发明人： Kazuaki TATSUMI , Yoshiki SOTA
IPC分类号： H01L23/498 , H05K1/05 , H01L21/50
CPC分类号： H05K3/3452 , H01L23/49827 , H01L23/49838 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/73 , H01L2224/32057 , H01L2224/32225 , H01L2224/45015 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2224/83385 , H01L2924/01005 , H01L2924/01006 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/15151 , H01L2924/15183 , H01L2924/15311 , H01L2924/181 , H01L2924/20752 , H01L2924/3511 , H05K1/112 , H05K3/0094 , H05K3/427 , H05K2201/0959 , H05K2201/0989 , H05K2201/10734 , H05K2203/0585 , H05K2203/1178 , H01L2924/00014 , H01L2924/3512 , H01L2924/00 , H01L2924/00012
摘要： The insulative wiring board of the present invention, with its both surfaces being covered with solder resist, includes at least one via hole in a semiconductor chip-mounting area penetrating the insulative wiring board, wherein conductor layers are electrically connected to each other via said at least one via hole. Further, the mounting area is covered with the solder resist, excluding said at least one via hole that penetrates the insulative wiring board. Therefore, it is possible to achieve an insulative wiring board that prevents defects caused by expansion occurred due to heating of moisture absorbed by the board, as well as reducing an area where a wiring cannot be provided.
摘要翻译：本发明的绝缘布线基板，其两面被阻焊剂覆盖，包括穿过绝缘布线板的半导体芯片安装区域中的至少一个通路孔，其中导体层经由所述导电层彼此电连接至少一个通孔。此外，除了穿过绝缘布线板的所述至少一个通孔之外，用阻焊剂覆盖安装区域。因此，可以实现防止由于板吸收的水分的加热而发生的膨胀引起的缺陷的绝缘布线板以及减少不能提供布线的区域。

4. 发明申请

US20100148311A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20100148311A1
公开(公告)日：2010-06-17
申请号：US12635000
申请日：2009-12-10
申请人： Koji MIYATA , Hiroyuki Nakanishi , Masahiro Okita , Kazuaki Tatsumi , Masato Yokobayashi
发明人： Koji MIYATA , Hiroyuki Nakanishi , Masahiro Okita , Kazuaki Tatsumi , Masato Yokobayashi
IPC分类号： H01L23/544
CPC分类号： H01L24/83 , H01L23/544 , H01L24/31 , H01L2223/5442 , H01L2223/54426 , H01L2224/16 , H01L2224/83194 , H01L2224/838 , H01L2924/00011 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/0781 , H01L2924/3512 , H01L2924/00 , H01L2224/0401
摘要： Patterns provided on a surface of a substrate include an adhesion area pattern and one or more non-adhesion area patterns. A chip electrode on a backside of a semiconductor chip is attached to the adhesion area pattern by a conductive adhesive. Consequently, an area of patterns subjected to gold plating that is stable in a steady state is smaller in a substrate of the present invention than in a conventional substrate, resulting in reduction in costs. Further, the chip electrode is attached to the adhesion area pattern by a conductive adhesive in a liquid form. Consequently, a semiconductor device of the present invention allows reducing use of an expensive conductive adhesive compared with a conventional semiconductor device, resulting in reduction in costs.
摘要翻译：设置在基板的表面上的图案包括粘合区域图案和一个或多个非粘合区域图案。半导体芯片背面的芯片电极通过导电粘合剂附着在粘合区域图案上。因此，在本发明的基板中，与常规基板相比，在稳定状态下稳定的金镀层图案较小，导致成本降低。此外，芯片电极通过导电粘合剂以液体形式附着到粘附区域图案上。因此，与传统的半导体器件相比，本发明的半导体器件能够减少使用昂贵的导电粘合剂，从而降低成本。

5. 发明授权

US08436456B2 Wiring board, semiconductor device and method for manufacturing semiconductor device 有权
标题翻译：接线板，半导体器件及半导体器件的制造方法
公开(公告)号：US08436456B2
公开(公告)日：2013-05-07
申请号：US12988697
申请日：2009-03-16
申请人： Yoshiki Sota , Kazuaki Tatsumi
发明人： Yoshiki Sota , Kazuaki Tatsumi
IPC分类号： H01L23/02 , H01L21/00
CPC分类号： H01L23/49838 , H01L23/13 , H01L23/564 , H01L24/45 , H01L24/48 , H01L24/73 , H01L2224/32225 , H01L2224/45015 , H01L2224/451 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48227 , H01L2224/48228 , H01L2224/73265 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/01322 , H01L2924/12041 , H01L2924/15151 , H01L2924/15311 , H01L2924/181 , H05K3/305 , H05K3/3452 , H05K2201/09072 , H05K2201/09772 , H05K2201/0989 , H05K2203/1178 , Y02P70/613 , H01L2924/00014 , H01L2924/00 , H01L2924/00012 , H01L2924/20752 , H01L2924/20753 , H01L2924/00015
摘要： A wiring board (10) of the present invention includes: a through hole (11b), provided in a semiconductor chip mounted region (15), penetrating the wiring board (10); and a groove pattern (13), provided on a solder resist (9) formed on the semiconductor chip mounted region (15), leading to the through hole (11b). The foregoing configuration makes it possible to guide, via the groove pattern (13) to the through hole (11b), moisture that collects in the semiconductor chip mounted region (15) and therefore to effectively discharge the moisture from the semiconductor chip mounted region (15). Thus, a semiconductor device (30) that employs the wiring board (10) does not suffer from vaporization and expansion, inside of it, due to heat that is applied at the time of manufacturing the semiconductor device (30) and at the time of mounting the semiconductor device (30) on a mount substrate. It is therefore possible to reduce expansion of the semiconductor device.
摘要翻译：本发明的布线基板（10）具备：贯通所述布线基板（10）的贯通孔（11b），设置在半导体芯片安装区域（15）中。以及设置在形成在半导体芯片安装区域（15）上的阻焊剂（9）上的通向通孔（11b）的凹槽图案（13）。上述构造使得可以经由凹槽图案（13）引导到通孔（11b），其收集在半导体芯片安装区域（15）中的湿气，并且因此有效地从半导体芯片安装区域排出水分（ 15）。因此，采用该布线基板（10）的半导体装置（30）在制造半导体装置（30）时由于加热而在其内部不会发生汽化膨胀，将半导体器件（30）安装在安装基板上。因此可以减少半导体器件的膨胀。

6. 发明授权

US08269353B2 Semiconductor device having a plurality of adhesion area patterns and one or more non-adhesion area patterns 有权
标题翻译：具有多个粘附区域图案和一个或多个非粘合区域图案的半导体器件
公开(公告)号：US08269353B2
公开(公告)日：2012-09-18
申请号：US12635000
申请日：2009-12-10
申请人： Koji Miyata , Hiroyuki Nakanishi , Masahiro Okita , Kazuaki Tatsumi , Masato Yokobayashi
发明人： Koji Miyata , Hiroyuki Nakanishi , Masahiro Okita , Kazuaki Tatsumi , Masato Yokobayashi
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L24/83 , H01L23/544 , H01L24/31 , H01L2223/5442 , H01L2223/54426 , H01L2224/16 , H01L2224/83194 , H01L2224/838 , H01L2924/00011 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/0781 , H01L2924/3512 , H01L2924/00 , H01L2224/0401
摘要： Patterns provided on a surface of a substrate include an adhesion area pattern and one or more non-adhesion area patterns. A chip electrode on a backside of a semiconductor chip is attached to the adhesion area pattern by a conductive adhesive. Consequently, an area of patterns subjected to gold plating that is stable in a steady state is smaller in a substrate of the present invention than in a conventional substrate, resulting in reduction in costs. Further, the chip electrode is attached to the adhesion area pattern by a conductive adhesive in a liquid form. Consequently, a semiconductor device of the present invention allows reducing use of an expensive conductive adhesive compared with a conventional semiconductor device, resulting in reduction in costs.
摘要翻译：设置在基板的表面上的图案包括粘合区域图案和一个或多个非粘合区域图案。半导体芯片背面的芯片电极通过导电粘合剂附着在粘合区域图案上。因此，在本发明的基板中，与常规基板相比，在稳定状态下稳定的金镀层图案较小，导致成本降低。此外，芯片电极通过导电粘合剂以液体形式附着到粘附区域图案上。因此，与传统的半导体器件相比，本发明的半导体器件能够减少使用昂贵的导电粘合剂，从而降低成本。

7. 发明授权

US4508953A Method of multi-layer welding 失效
标题翻译：多层焊接方法
公开(公告)号：US4508953A
公开(公告)日：1985-04-02
申请号：US487687
申请日：1983-04-22
申请人： Tsudoi Murakami , Shoji Nasu , Kazuaki Tatsumi , Yasuhide Nagahama
发明人： Tsudoi Murakami , Shoji Nasu , Kazuaki Tatsumi , Yasuhide Nagahama
IPC分类号： B23K9/02 , B23K9/12
CPC分类号： B23K9/0216
摘要： A method of multi-layer welding in which the welding operation is performed according to a path of welding defined by interpolating a plurality of instructed points by a suitable line, the method being characterized by storing in a memory device the coordinates actually passed by a welding torch in the welding operation of the first layer at the instructed points and determining the welding path of the second and succeeding layers by adding a predetermined amount of shift to the actual detected coordinates stored in the memory device at the instructed points and interpolating the shifted coordinates by a suitable line. According to another aspect of the present invention, therefor provided is a method for controlling the locus of operation in the second and succeeding layers in a multi-layer welding operation by a teach/playback type robot including an arithmetic control mechanism the method being characterized by teaching an arcuate locus of operation of the first layer; utilizing as a parameter a shift width corresponding to the arcuate bead to be formed in the second and succeeding layers through an external input member; determining the direction of shift of the second and succeeding layers by calculating the inner product of the directional vector of a welding torch according to the teaching data of the first layer and a directional vector from a point on the arcuate locus of operation to the center of the arc; and calculating the locus of operation of the second or a succeeding layer from the shift direction and width by the arithmetic control mechanism.
摘要翻译：一种多层焊接方法，其中根据通过适当的线插入多个指示点所限定的焊接路径执行焊接操作，该方法的特征在于，在存储装置中存储通过焊接实际通过的坐标在指示点处焊接第一层的焊炬，并且通过在指示点处对存储在存储装置中的实际检测到的坐标加上预定量的位移来确定第二层和后层的焊接路径，并且内插移位的坐标通过合适的线。根据本发明的另一方面，提供了一种用于通过包括算术控制机构的教导/重放型机器人在多层焊接操作中控制第二层和后层中的操作轨迹的方法，该方法的特征在于教授第一层的弧形轨迹; 利用与通过外部输入构件形成在第二层和后层中的弓形凸缘相对应的移位宽度作为参数; 通过根据第一层的教学数据计算焊炬的方向矢量的内积和从弓形操作轨迹上的点到方向矢量的方向矢量来确定第二层和后层的移位方向电弧并且通过算术控制机构从移位方向和宽度计算第二层或后层的工作轨迹。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式