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1. 发明授权

US08957480B2 Semiconductor device including dummy transistors with reduced off-leakage current 有权
标题翻译：半导体器件包括具有减少的漏电流的虚拟晶体管
公开(公告)号：US08957480B2
公开(公告)日：2015-02-17
申请号：US14003225
申请日：2011-03-04
申请人： Kazuaki Deguchi , Yasuo Morimoto , Masao Ito
发明人： Kazuaki Deguchi , Yasuo Morimoto , Masao Ito
IPC分类号： H01L29/00 , H01L27/088 , H01L21/8234 , H01L27/02
CPC分类号： H01L27/088 , H01L21/823425 , H01L27/0207 , H01L29/7846
摘要： In a semiconductor device, an active region includes: a first impurity region to which a predetermined voltage is applied; second and third impurity regions forming a pair of conductive electrodes of an insulated gate field effect transistor; and at least one impurity region disposed between the first and second impurity regions. A voltage that causes electrical conduction between the second and third impurity regions is applied to a gate electrode disposed between the second and third impurity regions. All gate electrodes disposed between the first and second impurity regions are configured to be electrically connected to the first impurity region constantly. All impurity regions disposed between the first and second impurity regions are electrically isolated from the first and second impurity regions and maintained in a floating state.
摘要翻译：在半导体器件中，有源区包括：施加预定电压的第一杂质区; 形成绝缘栅场效应晶体管的一对导电电极的第二和第三杂质区; 以及设置在第一和第二杂质区域之间的至少一个杂质区域。将引起第二和第三杂质区之间导电的电压施加到设置在第二和第三杂质区之间的栅电极。设置在第一和第二杂质区域之间的所有栅极电极被配置为恒定地电连接到第一杂质区域。设置在第一和第二杂质区域之间的所有杂质区域与第一和第二杂质区域电隔离并保持在浮置状态。

2. 发明申请

US20130334609A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20130334609A1
公开(公告)日：2013-12-19
申请号：US14003225
申请日：2011-03-04
申请人： Kazuaki Deguchi , Yasuo Morimoto , Masao Ito
发明人： Kazuaki Deguchi , Yasuo Morimoto , Masao Ito
IPC分类号： H01L27/088
CPC分类号： H01L27/088 , H01L21/823425 , H01L27/0207 , H01L29/7846
摘要： In a semiconductor device, an active region includes: a first impurity region to which a predetermined voltage is applied; second and third impurity regions forming a pair of conductive electrodes of an insulated gate field effect transistor; and at least one impurity region disposed between the first and second impurity regions. A voltage that causes electrical conduction between the second and third impurity regions is applied to a gate electrode disposed between the second and third impurity regions. All gate electrodes disposed between the first and second impurity regions are configured to be electrically connected to the first impurity region constantly. All impurity regions disposed between the first and second impurity regions are electrically isolated from the first and second impurity regions and maintained in a floating state.
摘要翻译：在半导体器件中，有源区包括：施加预定电压的第一杂质区; 形成绝缘栅场效应晶体管的一对导电电极的第二和第三杂质区; 以及设置在第一和第二杂质区域之间的至少一个杂质区域。将引起第二和第三杂质区之间导电的电压施加到设置在第二和第三杂质区之间的栅电极。设置在第一和第二杂质区域之间的所有栅极电极被配置为恒定地电连接到第一杂质区域。设置在第一和第二杂质区域之间的所有杂质区域与第一和第二杂质区域电隔离并保持在浮置状态。

3. 发明授权

US07675363B2 Differential amplifier circuit and A/D converter 有权
标题翻译：差分放大器电路和A / D转换器
公开(公告)号：US07675363B2
公开(公告)日：2010-03-09
申请号：US12155278
申请日：2008-06-02
申请人： Kazuaki Deguchi , Takahiro Miki
发明人： Kazuaki Deguchi , Takahiro Miki
IPC分类号： H03F3/45
CPC分类号： H03F3/45183 , H03F3/45659 , H03F2200/453 , H03F2203/45082 , H03F2203/45424
摘要： PMOS transistors are interposed parallel to each other between a node, which is a first output part, and a power supply; and PMOS transistors are interposed in parallel to each other between a node, which is a second output part, and the power supply. Output voltages in time of a balanced state in which an input potential difference between an input voltage and a reference voltage is “0” are both set to a reference output common voltage by a replica circuit and a comparator. The reference output common voltage of the replica circuit is set so that the potential difference between the power supply voltage and the output common voltage becomes a value lower than a threshold voltage of the diode connected PMOS transistors.
摘要翻译： PMOS晶体管在作为第一输出部分的节点和电源之间彼此平行地插入; 并且在作为第二输出部分的节点和电源之间彼此并联插入PMOS晶体管。通过复制电路和比较器将输入电压和参考电压之间的输入电位差为“0”的平衡状态的输出电压都设定为基准输出公共电压。复制电路的参考输出公共电压被设定为使得电源电压和输出公共电压之间的电位差成为低于连接有二极管的PMOS晶体管的阈值电压的值。

4. 发明申请

US20080303592A1 Differential amplifier circuit and A/D converter 有权
标题翻译：差分放大器电路和A / D转换器
公开(公告)号：US20080303592A1
公开(公告)日：2008-12-11
申请号：US12155278
申请日：2008-06-02
申请人： Kazuaki Deguchi , Takahiro Miki
发明人： Kazuaki Deguchi , Takahiro Miki
IPC分类号： H03F3/45
CPC分类号： H03F3/45183 , H03F3/45659 , H03F2200/453 , H03F2203/45082 , H03F2203/45424
摘要： PMOS transistors are interposed parallel to each other between a node, which is a first output part, and a power supply; and PMOS transistors are interposed in parallel to each other between a node, which is a second output part, and the power supply. Output voltages in time of a balanced state in which an input potential difference between an input voltage and a reference voltage is “0” are both set to a reference output common voltage by a replica circuit and a comparator. The reference output common voltage of the replica circuit is set so that the potential difference between the power supply voltage and the output common voltage becomes a value lower than a threshold voltage of the diode connected PMOS transistors.
摘要翻译： PMOS晶体管在作为第一输出部分的节点和电源之间彼此平行地插入; 并且在作为第二输出部分的节点和电源之间彼此并联插入PMOS晶体管。通过复制电路和比较器将输入电压和参考电压之间的输入电位差为“0”的平衡状态的输出电压都设定为基准输出公共电压。复制电路的参考输出公共电压被设定为使得电源电压和输出公共电压之间的电位差成为低于连接有二极管的PMOS晶体管的阈值电压的值。

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