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1. 发明授权

US08084304B2 Method for preventing gate oxide damage of a trench MOSFET during wafer processing while adding an ESD protection module atop 有权
标题翻译：在晶片处理期间防止沟槽MOSFET的栅极氧化物损伤的方法，同时在其上添加ESD保护模块
公开(公告)号：US08084304B2
公开(公告)日：2011-12-27
申请号：US12790813
申请日：2010-05-29
申请人： Mengyu Pan , Zengyi He , Kaiyu Chen
发明人： Mengyu Pan , Zengyi He , Kaiyu Chen
IPC分类号： H01L21/20 , H01L21/336
CPC分类号： H01L29/7813 , H01L21/8221 , H01L27/0255 , H01L29/66734 , H01L29/7808 , H01L29/7811 , H01L2924/0002 , H01L2924/00
摘要： A method for preventing gate oxide damage of a trench MOSFET during wafer processing while adding an ESD protection module atop the trench MOSFET includes fabricate numerous trench MOSFETs on a wafer; add a Si3N4 isolation layer, capable of preventing the LTO patterning process from damaging the gate oxide, atop the wafer; add numerous ESD protection modules atop the Si3N4 isolation layer.
摘要翻译：在晶片处理期间防止沟槽MOSFET的栅极氧化物损伤的方法同时在沟槽MOSFET上方添加ESD保护模块包括在晶片上制造多个沟槽MOSFET; 添加能够防止LTO图案化过程损坏栅极氧化物的Si 3 N 4隔离层; 在Si3N4隔离层顶部添加许多ESD保护模块。

2. 发明申请

US20110018054A1 Method for Preventing Gate Oxide Damage of a Trench MOSFET during Wafer Processing while Adding an ESD Protection Module Atop 有权
标题翻译：在添加ESD保护模块的同时，在晶圆处理期间防止沟槽MOSFET的栅极氧化物损坏的方法
公开(公告)号：US20110018054A1
公开(公告)日：2011-01-27
申请号：US12790813
申请日：2010-05-29
申请人： Mengyu Pan , Zengyi He , Kaiyu Chen
发明人： Mengyu Pan , Zengyi He , Kaiyu Chen
IPC分类号： H01L27/06 , H01L21/311 , H01L21/28 , H01L29/78
CPC分类号： H01L29/7813 , H01L21/8221 , H01L27/0255 , H01L29/66734 , H01L29/7808 , H01L29/7811 , H01L2924/0002 , H01L2924/00
摘要： A method and device structure are disclosed for preventing gate oxide damage of a trench MOSFET during wafer processing while adding an ESD protection module atop the trench MOSFET. The ESD protection module has a low temperature oxide (LTO) bottom layer whose patterning process is found to cause the gate oxide damage. The method includes:a) Fabricate numerous trench MOSFETs on a wafer.b) Add a Si3N4 isolation layer, capable of preventing the LTO patterning process from damaging the gate oxide, atop the wafer.c) Add numerous ESD protection modules atop the Si3N4 isolation layer.d) Remove those portions of the Si3N4 isolation layer that are not beneath the ESD protection modules.In one embodiment, hydrofluoric acid is used as a first etchant for patterning the LTO while hot phosphoric acid is used as a second etchant for removing portions of the Si3N4 isolation layer.
摘要翻译：公开了一种方法和器件结构，用于在晶片处理期间防止沟槽MOSFET的栅极氧化物损坏，同时在沟槽MOSFET顶部添加ESD保护模块。 ESD保护模块具有低温氧化物（LTO）底层，其图案化过程被发现导致栅极氧化物损伤。该方法包括：a）在晶片上制造多个沟槽MOSFET。 b）添加Si3N4隔离层，能够防止LTO图案化工艺损坏晶片顶部的栅极氧化物。 c）在Si3N4隔离层顶部添加许多ESD保护模块。 d）拆下不在ESD保护模块下方的Si3N4隔离层的那些部分。在一个实施方案中，氢氟酸用作图案化LTO的第一蚀刻剂，而使用热磷酸作为用于除去Si 3 N 4隔离层的部分的第二蚀刻剂。

3. 发明申请

US20130159680A1 SYSTEMS, METHODS, AND COMPUTER PROGRAM PRODUCTS FOR PARALLELIZING LARGE NUMBER ARITHMETIC 审中-公开
标题翻译：用于并行大数字算术的系统，方法和计算机程序产品
公开(公告)号：US20130159680A1
公开(公告)日：2013-06-20
申请号：US13330359
申请日：2011-12-19
申请人： Wei-yu Chen , Guei-yuan Lueh , Kaiyu Chen , Xiaozhu Kang
发明人： Wei-yu Chen , Guei-yuan Lueh , Kaiyu Chen , Xiaozhu Kang
IPC分类号： G06F9/302 , G06F9/315
CPC分类号： G06F9/30021 , G06F9/30014 , G06F9/30036
摘要： Methods, systems, and computer program products for the performance of arithmetic operations on large numbers. The addition of large numbers may be parallelized by adding corresponding sections of the numbers in parallel. The multiplication of large numbers may be accomplished by applying a multiplier to a multiplicand after the latter is divided into sections, where the multiplication of the sections is performed in parallel. Products for each section are saved in high and low order vectors, which may then be aligned and added. The comparison of two large numbers may be performed by comparing the numbers, section by section, in parallel. In an embodiment, these processes may be performed in a graphics processing unit (GPU) having multiple cores. In an embodiment, such a GPU may be integrated into a larger die that also incorporates one or more conventional central processing unit (CPU) cores.
摘要翻译：方法，系统和计算机程序产品，用于大量数字运算。通过并行添加数字的相应部分可以并行添加大量数字。大数乘法可以通过在乘法器被划分成段之后对乘法器应用乘法器来实现，其中段的乘法并行执行。每个部分的产品保存在高阶和低阶向量中，然后可以对齐和添加。两个大数字的比较可以通过并行比较数字来进行。在一个实施例中，这些处理可以在具有多个核的图形处理单元（GPU）中执行。在一个实施例中，这样的GPU可以集成到还包括一个或多个常规中央处理单元（CPU）核心的更大的管芯中。

4. 发明授权

US07728385B2 Trench MOSFET with an ONO insulating layer sandwiched between an ESD protection module atop and a semiconductor substrate 有权
标题翻译：沟槽MOSFET，其中ONO绝缘层夹在顶部的ESD保护模块和半导体衬底之间
公开(公告)号：US07728385B2
公开(公告)日：2010-06-01
申请号：US12507772
申请日：2009-07-22
申请人： Mengyu Pan , Zengyi He , Kaiyu Chen
发明人： Mengyu Pan , Zengyi He , Kaiyu Chen
IPC分类号： H01L23/62
CPC分类号： H01L29/7813 , H01L21/8221 , H01L27/0255 , H01L29/66734 , H01L29/7808 , H01L29/7811 , H01L2924/0002 , H01L2924/00
摘要： A device structure is disclosed for preventing gate oxide damage of a trench MOSFET during wafer processing while adding an ESD protection module atop the trench MOSFET. The ESD protection module has a low temperature oxide (LTO) bottom layer whose patterning process was found to cause the gate oxide damage before. The present invention structure includes a semiconductor substrate having an active area and a termination area; numerous trench MOSFET cells disposed in the active area; numerous electrostatic discharge (ESD) diodes disposed above the semiconductor substrate in the termination area; and an insulation layer comprising Oxide/Nitride/Oxide (ONO) sandwiched between the ESD diodes and the semiconductor substrate. In one embodiment, the active area does not contain the ONO insulation layer.
摘要翻译：公开了一种器件结构，用于在晶片处理期间防止沟槽MOSFET的栅极氧化物损坏，同时在沟槽MOSFET顶部添加ESD保护模块。 ESD保护模块具有低温氧化物（LTO）底层，其图案化工艺被发现导致栅极氧化物损伤。本发明的结构包括具有有源区和端接区的半导体衬底; 设置在有源区中的多个沟槽MOSFET电池; 设置在终端区域中的半导体衬底上方的许多静电放电（ESD）二极管; 以及夹在ESD二极管和半导体衬底之间的包含氧化物/氮化物/氧化物（ONO）的绝缘层。在一个实施例中，有源区不包含ONO绝缘层。

5. 发明申请

US20180096446A1 Graphics Processor Register Renaming Mechanism 审中-公开
公开(公告)号：US20180096446A1
公开(公告)日：2018-04-05
申请号：US15281276
申请日：2016-09-30
申请人： Kaiyu Chen , Guei-Yuan Lueh , Subramaniam Maiyuran
发明人： Kaiyu Chen , Guei-Yuan Lueh , Subramaniam Maiyuran
IPC分类号： G06T1/20 , G06T1/60 , G06T15/00 , G06T15/80
摘要： A processing apparatus is described. The apparatus includes a graphics processing unit (GPU), including a plurality of execution units to process graphics context data and a register file having a plurality of registers to store the graphics context data; and register renaming logic to facilitate dynamic renaming of the plurality of registers by logically partitioning the plurality of registers in the register file into a set of fixed registers and a set of shared registers.

6. 发明申请

US20090278199A1 Method for Preventing Gate Oxide Damage of a Trench MOSFET during Wafer Processing while Adding an ESD Protection Module Atop 有权
标题翻译：在添加ESD保护模块的同时，在晶圆处理期间防止沟槽MOSFET的栅极氧化物损坏的方法
公开(公告)号：US20090278199A1
公开(公告)日：2009-11-12
申请号：US12507772
申请日：2009-07-22
申请人： Mengyu Pan , Zengyi He , Kaiyu Chen
发明人： Mengyu Pan , Zengyi He , Kaiyu Chen
IPC分类号： H01L27/088
CPC分类号： H01L29/7813 , H01L21/8221 , H01L27/0255 , H01L29/66734 , H01L29/7808 , H01L29/7811 , H01L2924/0002 , H01L2924/00
摘要： A method and device structure are disclosed for preventing gate oxide damage of a trench MOSFET during wafer processing while adding an ESD protection module atop the trench MOSFET. The ESD protection module has a low temperature oxide (LTO) bottom layer whose patterning process is found to cause the gate oxide damage. The method includes: a) Fabricate numerous trench MOSFETs on a wafer. b) Add a Si3N4 isolation layer, capable of preventing the LTO patterning process from damaging the gate oxide, atop the wafer. c) Add numerous ESD protection modules atop the Si3N4 isolation layer. d) Remove those portions of the Si3N4 isolation layer that are not beneath the ESD protection modules. In one embodiment, hydrofluoric acid is used as a first etchant for patterning the LTO while hot phosphoric acid is used as a second etchant for removing portions of the Si3N4 isolation layer.
摘要翻译：公开了一种方法和器件结构，用于在晶片处理期间防止沟槽MOSFET的栅极氧化物损坏，同时在沟槽MOSFET顶部添加ESD保护模块。 ESD保护模块具有低温氧化物（LTO）底层，其图案化过程被发现导致栅极氧化物损伤。该方法包括：a）在晶片上制造多个沟槽MOSFET。 b）添加Si3N4隔离层，能够防止LTO图案化工艺损坏晶片顶部的栅极氧化物。 c）在Si3N4隔离层顶部添加许多ESD保护模块。 d）拆下不在ESD保护模块下方的Si3N4隔离层的那些部分。在一个实施方案中，氢氟酸用作图案化LTO的第一蚀刻剂，而使用热磷酸作为用于除去Si 3 N 4隔离层的部分的第二蚀刻剂。

7. 发明授权

US07585705B2 Method for preventing gate oxide damage of a trench MOSFET during wafer processing while adding an ESD protection module atop 有权
公开(公告)号：US07585705B2
公开(公告)日：2009-09-08
申请号：US11947750
申请日：2007-11-29
申请人： Mengyu Pan , Zengyi He , Kaiyu Chen
发明人： Mengyu Pan , Zengyi He , Kaiyu Chen
IPC分类号： H01L21/20
CPC分类号： H01L29/7813 , H01L21/8221 , H01L27/0255 , H01L29/66734 , H01L29/7808 , H01L29/7811 , H01L2924/0002 , H01L2924/00
摘要： A method and device structure are disclosed for preventing gate oxide damage of a trench MOSFET during wafer processing while adding an ESD protection module atop the trench MOSFET. The ESD protection module has a low temperature oxide (LTO) bottom layer whose patterning process is found to cause the gate oxide damage. The method includes: a) Fabricate numerous trench MOSFETs on a wafer. b) Add a Si3N4 isolation layer, capable of preventing the LTO patterning process from damaging the gate oxide, atop the wafer. c) Add numerous ESD protection modules atop the Si3N4 isolation layer. d) Remove those portions of the Si3N4 isolation layer that are not beneath the ESD protection modules. In one embodiment, hydrofluoric acid is used as a first etchant for patterning the LTO while hot phosphoric acid is used as a second etchant for removing portions of the Si3N4 isolation layer.

8. 发明申请

US20090140333A1 Method for preventing gate oxide damage of a trench MOSFET during wafer processing while adding an ESD protection module atop 有权
标题翻译：在晶片处理期间防止沟槽MOSFET的栅极氧化物损伤的方法，同时在其上添加ESD保护模块
公开(公告)号：US20090140333A1
公开(公告)日：2009-06-04
申请号：US11947750
申请日：2007-11-29
申请人： Mengyu Pan , Zengyi He , Kaiyu Chen
发明人： Mengyu Pan , Zengyi He , Kaiyu Chen
IPC分类号： H01L27/06 , H01L21/8234 , H01L21/329
CPC分类号： H01L29/7813 , H01L21/8221 , H01L27/0255 , H01L29/66734 , H01L29/7808 , H01L29/7811 , H01L2924/0002 , H01L2924/00
摘要： A method and device structure are disclosed for preventing gate oxide damage of a trench MOSFET during wafer processing while adding an ESD protection module atop the trench MOSFET. The ESD protection module has a low temperature oxide (LTO) bottom layer whose patterning process is found to cause the gate oxide damage. The method includes:a) Fabricate numerous trench MOSFETs on a wafer. b) Add a Si3N4 isolation layer, capable of preventing the LTO patterning process from damaging the gate oxide, atop the wafer. c) Add numerous ESD protection modules atop the Si3N4 isolation layer. d) Remove those portions of the Si3N4 isolation layer that are not beneath the ESD protection modules. In one embodiment, hydrofluoric acid is used as a first etchant for patterning the LTO while hot phosphoric acid is used as a second etchant for removing portions of the Si3N4 isolation layer.
摘要翻译：公开了一种方法和器件结构，用于在晶片处理期间防止沟槽MOSFET的栅极氧化物损坏，同时在沟槽MOSFET顶部添加ESD保护模块。 ESD保护模块具有低温氧化物（LTO）底层，其图案化过程被发现导致栅极氧化物损伤。该方法包括：a）在晶片上制造多个沟槽MOSFET。 b）添加Si3N4隔离层，能够防止LTO图案化工艺损坏晶片顶部的栅极氧化物。 c）在Si3N4隔离层顶部添加许多ESD保护模块。 d）拆下不在ESD保护模块下方的Si3N4隔离层的那些部分。在一个实施方案中，氢氟酸用作图案化LTO的第一蚀刻剂，而热磷酸用作用于除去Si 3 N 4隔离层的部分的第二蚀刻剂。

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