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1. 发明授权

US08811088B2 Method of reading memory cells with different threshold voltages without variation of word line voltage and nonvolatile memory device using the same 有权
标题翻译：使用不同字线电压的不同阈值电压读取存储单元的方法和使用其的非易失性存储器件
公开(公告)号：US08811088B2
公开(公告)日：2014-08-19
申请号：US13608030
申请日：2012-09-10
申请人： Sang-Hyun Joo , Kiwhan Song , Ju Seok Lee , Kihwan Choi
发明人： Sang-Hyun Joo , Kiwhan Song , Ju Seok Lee , Kihwan Choi
IPC分类号： G11C16/26
CPC分类号： G11C16/26 , G11C11/5642 , G11C16/0483 , G11C16/08 , G11C2211/563
摘要： A soft-decision read method of a nonvolatile memory device includes receiving a soft-decision read command, applying a read voltage to a selected word line, pre-charging bit lines respectively connected to selected memory cells of the selected word line, continuously sensing states of the selected memory cells. The pre-charged voltages of the bit lines and the read voltage supplied to the selected word line are not varied during the sensing states of the selected memory cells.
摘要翻译：非易失性存储器件的软判决读取方法包括：接收软判决读命令，将读电压施加到所选择的字线，对分别连接到所选字线的选定存储单元的位线进行预充电，连续检测状态的所选存储单元。提供给所选字线的位线的预充电电压和读取电压在所选存储单元的感测状态期间不改变。

2. 发明申请

US20140010021A1 NON-VOLATILE MEMORY DEVICE AND READ METHOD THEREOF 有权
标题翻译：非易失性存储器件及其读取方法
公开(公告)号：US20140010021A1
公开(公告)日：2014-01-09
申请号：US14023787
申请日：2013-09-11
申请人： Ji-Sang LEE , Kihwan CHOI
发明人： Ji-Sang LEE , Kihwan CHOI
IPC分类号： G11C16/26
CPC分类号： G11C16/26 , G11C11/5642 , G11C16/0483 , G11C16/3418
摘要： In one embodiment, the method includes receiving a request to read data stored in a first memory cell associated with a first word line, and performing a first read operation on at least one memory cell associated with a second word line in response to the request. The second word line follows the first word line in a word line programming order, and the first read operation is performed over a first time period. The method further includes performing a second read operation on the first memory cell based on output from the first read operation. The second read operation is performed for a second time period, and the first time period is shorter than the second time period if output from performing the first read operation indicates the first memory cell is not coupled.
摘要翻译：在一个实施例中，该方法包括接收读取存储在与第一字线相关联的第一存储器单元中的数据的请求，以及响应于该请求对与第二字线相关联的至少一个存储器单元执行第一读取操作。第二字线在字线编程顺序中跟随第一字线，并且在第一时间段执行第一读取操作。该方法还包括基于来自第一读取操作的输出对第一存储器单元执行第二读取操作。如果从执行第一读取操作的输出指示第一存储器单元没有耦合，则第二次读取操作执行第二时间段，并且第一时间段比第二时间段短。

3. 发明申请

US20100091576A1 Nonvolatile memory device, program method and precharge voltage boosting method thereof, and memory system including the nonvolatile memory device 有权
标题翻译：非易失性存储器件，其编程方法和预充电升压方法以及包括非易失性存储器件的存储器系统
公开(公告)号：US20100091576A1
公开(公告)日：2010-04-15
申请号：US12587803
申请日：2009-10-13
申请人： Ohsuk Kwon , Kihwan Choi
发明人： Ohsuk Kwon , Kihwan Choi
IPC分类号： G11C16/06 , G11C16/04
CPC分类号： G11C16/3418 , G11C16/0483 , G11C16/10 , G11C16/3427
摘要： A method of programming a nonvolatile memory device according to the present invention includes precharging bit lines according to data loaded in page buffers; electrically connecting the precharged bit lines to channels corresponding to the bit lines, respectively, to charge the channels; and applying a word line voltage for a program after charging the channels. A channel voltage boosting of each of the channels is determined according to data loaded in adjacent page buffers.
摘要翻译：根据本发明的非易失性存储器件的编程方法包括根据加载在页缓冲器中的数据预充电位线; 将预充电位线分别电连接到与位线对应的通道，以对通道充电; 以及在对频道充电之后对节目应用字线电压。根据加载在相邻页面缓冲器中的数据来确定每个通道的通道升压。

4. 发明授权

US06780098B2 Regulator for air outlet 有权
标题翻译：出风口调节器
公开(公告)号：US06780098B2
公开(公告)日：2004-08-24
申请号：US10359161
申请日：2003-02-06
申请人： Ryuhei Nishida , Kihwan Choi
发明人： Ryuhei Nishida , Kihwan Choi
IPC分类号： F24F1315
CPC分类号： B60H1/3414 , B60H2001/3478 , F24F13/15 , F24F2013/1446
摘要： A regulator for regulating airflow through an air outlet includes a plurality of louver blades integrated with axis portions supported at bearing holes and interconnected through an interlocking member; a supporting plate with the bearing holes attached to an air outlet; and an elastic portion provided on the supporting plate to be capable of deforming along an axis of the louver blades. Also, the regulator may include a damper; a manual operating member for tilting the louver blades and damper; and two gears engaging each other and disposed at an interconnecting portion between the manual operating member and the damper. One of the gears is formed in two portions separated along an axis and provided coaxially. The two portions have slightly shifted pitch, and are able to displace with each other in a circumferential direction with elasticity.
摘要翻译：用于调节通过空气出口的气流的调节器包括多个百叶窗叶片，其与轴承部分一体地支撑在轴承孔上并通过互锁构件相互连接; 支撑板，其具有附接到出气口的轴承孔; 以及设置在所述支撑板上以能够沿着所述百叶窗叶片的轴线变形的弹性部分。此外，调节器可以包括阻尼器; 用于倾斜百叶窗和阻尼器的手动操作构件; 以及两个齿轮彼此啮合并且设置在手动操作构件和阻尼器之间的互连部分处。齿轮中的一个形成为沿着轴线分开并且同轴地设置的两部分。这两个部分具有略微偏移的间距，并且能够在弹性方向上沿周向相互位移。

5. 发明申请

US20150179271A1 NONVOLATILE MEMORY DEVICE AND METHOD OF ERASING NONVOLATILE MEMORY DEVICE 有权
标题翻译：非易失性存储器件和非易失性存储器件的擦除方法
公开(公告)号：US20150179271A1
公开(公告)日：2015-06-25
申请号：US14501352
申请日：2014-09-30
申请人： SANG-WAN NAM , KANG-BIN LEE , KIHWAN CHOI
发明人： SANG-WAN NAM , KANG-BIN LEE , KIHWAN CHOI
IPC分类号： G11C16/16 , G11C11/16 , G11C13/00
CPC分类号： G11C16/16 , G11C11/16 , G11C16/0483
摘要： A method is provided for erasing a nonvolatile memory device, including multiple memory blocks formed in a direction perpendicular to a substrate, each memory block having multiple strings connected to a bit line. The method includes selecting a memory block to be erased using a power supply voltage; unselecting a remaining memory block, other than the selected memory block, using a negative voltage; setting a bias condition to reduce leakage currents of the unselected memory block; and performing an erase operation on the selected memory block.
摘要翻译：提供了一种用于擦除非易失性存储器件的方法，包括沿垂直于衬底的方向形成的多个存储块，每个存储块具有连接到位线的多个串。该方法包括使用电源电压选择要擦除的存储器块; 使用负电压取消选择存储块以外的剩余存储块; 设置偏置条件以减少未选择的存储器块的漏电流; 以及对所选存储块执行擦除操作。

6. 发明授权

US08717822B2 Non-volatile memory device and read method thereof 有权
标题翻译：非易失性存储器件及其读取方法
公开(公告)号：US08717822B2
公开(公告)日：2014-05-06
申请号：US14023787
申请日：2013-09-11
申请人： Ji-Sang Lee , Kihwan Choi
发明人： Ji-Sang Lee , Kihwan Choi
IPC分类号： G11C16/06
CPC分类号： G11C16/26 , G11C11/5642 , G11C16/0483 , G11C16/3418
摘要： In one embodiment, the method includes receiving a request to read data stored in a first memory cell associated with a first word line, and performing a first read operation on at least one memory cell associated with a second word line in response to the request. The second word line follows the first word line in a word line programming order, and the first read operation is performed over a first time period. The method further includes performing a second read operation on the first memory cell based on output from the first read operation. The second read operation is performed for a second time period, and the first time period is shorter than the second time period if output from performing the first read operation indicates the first memory cell is not coupled.
摘要翻译：在一个实施例中，该方法包括接收读取存储在与第一字线相关联的第一存储器单元中的数据的请求，以及响应于该请求对与第二字线相关联的至少一个存储器单元执行第一读取操作。第二字线在字线编程顺序中跟随第一字线，并且在第一时间段执行第一读取操作。该方法还包括基于来自第一读取操作的输出对第一存储器单元执行第二读取操作。如果从执行第一读取操作的输出指示第一存储器单元没有耦合，则第二次读取操作执行第二时间段，并且第一时间段比第二时间段短。

7. 发明授权

US08462558B2 Program and erase methods for nonvolatile memory 有权
标题翻译：非易失性存储器的编程和擦除方法
公开(公告)号：US08462558B2
公开(公告)日：2013-06-11
申请号：US12805500
申请日：2010-08-03
申请人： Seunghyun Moon , Kihwan Choi , Jaesung Sim , Jungdal Choi
发明人： Seunghyun Moon , Kihwan Choi , Jaesung Sim , Jungdal Choi
IPC分类号： G11C16/04 , G11C11/34
CPC分类号： G11C16/3404
摘要： Methods of programming or erasing a nonvolatile memory device having a charge storage layer including performing at least one unit programming or erasing loop, each unit programming or erasing loop including applying a programming pulse, an erasing pulse, a time delay, a soft erase pulse, soft programming pulse and/or a verifying pulse as a positive or negative voltage to a portion (for example, a word line or a substrate) of the nonvolatile memory device.
摘要翻译：编程或擦除具有电荷存储层的非易失性存储器件的方法包括执行至少一个单元编程或擦除循环，每个单元编程或擦除循环包括应用编程脉冲，擦除脉冲，时间延迟，软擦除脉冲，软编程脉冲和/或验证脉冲作为对非易失性存储器件的一部分（例如，字线或衬底）的正或负电压。

8. 发明授权

US08174906B2 Nonvolatile memory device, program method and precharge voltage boosting method thereof, and memory system including the nonvolatile memory device 有权
标题翻译：非易失性存储器件，其编程方法和预充电升压方法以及包括非易失性存储器件的存储器系统
公开(公告)号：US08174906B2
公开(公告)日：2012-05-08
申请号：US12587803
申请日：2009-10-13
申请人： Ohsuk Kwon , Kihwan Choi
发明人： Ohsuk Kwon , Kihwan Choi
IPC分类号： G11C7/10
CPC分类号： G11C16/3418 , G11C16/0483 , G11C16/10 , G11C16/3427
摘要： A method of programming a nonvolatile memory device according to the present invention includes precharging bit lines according to data loaded in page buffers; electrically connecting the precharged bit lines to channels corresponding to the bit lines, respectively, to charge the channels; and applying a word line voltage for a program after charging the channels. A channel voltage boosting of each of the channels is determined according to data loaded in adjacent page buffers.
摘要翻译：根据本发明的非易失性存储器件的编程方法包括根据加载在页缓冲器中的数据预充电位线; 将预充电位线分别电连接到与位线对应的通道，以对通道充电; 以及在对频道充电之后对节目应用字线电压。根据加载在相邻页面缓冲器中的数据来确定每个通道的通道升压。

9. 发明申请

US20100246258A1 NONVOLATILE MEMORY DEVICE AND RELATED METHOD OF PROGRAMMING 有权
标题翻译：非易失性存储器件及相关的编程方法
公开(公告)号：US20100246258A1
公开(公告)日：2010-09-30
申请号：US12719184
申请日：2010-03-08
申请人： Sung-Won YUN , Kihwan CHOI
发明人： Sung-Won YUN , Kihwan CHOI
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C11/5621 , G11C16/3436
摘要： A nonvolatile memory device comprises a memory cell array comprising a plurality of memory cells, a voltage generator configured to generate voltages to program the plurality of memory cells, and a control logic component configured to control the voltage generator to provide a plurality of program voltages to selected memory cells during successive iterations of a program loop. Wherein where memory cells corresponding to one logic state are judged to be program passed during a current iteration of the program loop, the control logic component controls the voltage generator such that a program voltage corresponding to the one logic state is skipped during subsequent iterations of the program loop.
摘要翻译：非易失性存储器件包括存储单元阵列，该存储单元阵列包括多个存储器单元，被配置为产生用于编程多个存储器单元的电压的电压发生器，以及控制逻辑元件，被配置为控制电压发生器以提供多个编程电压在程序循环的连续迭代期间选择存储单元。其中对应于一个逻辑状态的存储器单元在程序循环的当前迭代期间被判断为程序传递，控制逻辑部件控制电压发生器，使得在随后的迭代期间跳过对应于一个逻辑状态的编程电压程序循环。

10. 发明申请

US20100302861A1 Program and erase methods for nonvolatile memory 有权
公开(公告)号：US20100302861A1
公开(公告)日：2010-12-02
申请号：US12805500
申请日：2010-08-03
申请人： Seunghyun Moon , Kihwan Choi , Jaesung Sim , Jungdal Choi
发明人： Seunghyun Moon , Kihwan Choi , Jaesung Sim , Jungdal Choi
IPC分类号： G11C16/04 , G11C16/16
CPC分类号： G11C16/3404
摘要： Methods of programming or erasing a nonvolatile memory device having a charge storage layer including performing at least one unit programming or erasing loop, each unit programming or erasing loop including applying a programming pulse, an erasing pulse, a time delay, a soft erase pulse, soft programming pulse and/or a verifying pulse as a positive or negative voltage to a portion (for example, a word line or a substrate) of the nonvolatile memory device.

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