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1. 发明申请

US20080233912A1 METHOD AND APPARATUS FOR POWER REDUCTION FOR INTERCONNECT LINKS 有权
标题翻译：用于互连链路功率降低的方法和装置
公开(公告)号：US20080233912A1
公开(公告)日：2008-09-25
申请号：US11690759
申请日：2007-03-23
申请人： Mikal Hunsaker , Karthi R. Vadivelu
发明人： Mikal Hunsaker , Karthi R. Vadivelu
IPC分类号： H04B1/10
CPC分类号： H04L12/12 , Y02D50/40
摘要： A power reduction proposal for a receiver circuit that adheres to a plurality of defined states and masking logic to mask the output of the squelch receiver. Furthermore, the proposal utilizes and counters to count the various timeout conditions. Consequently, the squelch receiver consumes less power and can be either powered down or periodically enabled to allow for polling.
摘要翻译：一种用于接收多个定义状态的接收机电路的功率降低方案，并且屏蔽逻辑以屏蔽静噪接收机的输出。此外，该提案利用计数器来计数各种超时条件。因此，静噪接收器消耗较少的功率，并且可以断电或周期性地允许轮询。

2. 发明申请

US20190155371A1 LOW POWER DATA PROCESSING OFFLOAD USING EXTERNAL PLATFORM COMPONENT 审中-公开
公开(公告)号：US20190155371A1
公开(公告)日：2019-05-23
申请号：US16241476
申请日：2019-01-07
申请人： Kevin Zhenyu Zhu , Satheesh Chellappan , Mikal Hunsaker , Karthi R. Vadivelu , Kar Leong Wong
发明人： Kevin Zhenyu Zhu , Satheesh Chellappan , Mikal Hunsaker , Karthi R. Vadivelu , Kar Leong Wong
IPC分类号： G06F1/3293 , H04M1/73 , G06F13/42
摘要： Described is an apparatus comprising a first interface, a second interface, a third interface, and an interconnection fabric. The first interface may transfer a first stream of data traffic. The second interface, which may be an enhanced Serial Peripheral Interface (eSPI) interface, may transfer a second stream of data traffic and a third stream of data traffic. The third interface may transfer a fourth stream of data traffic. The interconnection fabric may couple the first interface to the second interface and may couple the second interface to the third interface. The second interface may initiate a transfer of an outbound data stream from one of the second stream of data traffic or the third stream of data traffic based on an available-space credit indicator. The second interface may receive an inbound data stream based upon the outbound data stream.

3. 发明申请

US20180130443A1 TECHNIQUES FOR MANAGING TRANSMISSION AND DISPLAY OF A DISPLAY DATA STREAM 审中-公开
公开(公告)号：US20180130443A1
公开(公告)日：2018-05-10
申请号：US15344257
申请日：2016-11-04
申请人： NAUSHEEN ANSARI , KARTHI R. VADIVELU , PAUL S. DIEFENBAUGH
发明人： NAUSHEEN ANSARI , KARTHI R. VADIVELU , PAUL S. DIEFENBAUGH
IPC分类号： G09G5/00 , G09G5/395
CPC分类号： G09G5/006 , G09G5/14 , G09G5/391 , G09G5/395 , G09G5/397 , G09G2310/08 , G09G2340/02 , G09G2340/0435 , G09G2360/12 , G09G2360/127 , G09G2360/18 , G09G2370/10 , G09G2370/12 , G09G2370/16
摘要： Computing devices and techniques for managing transmission and display of a display data stream are described. In one embodiment, for example, an apparatus may include at least one memory and logic for a display source, at least a portion of the logic comprised in hardware coupled to the at least one memory, the logic to generate display information comprising at least one frame for presentation at a display panel operably coupled to a display sink, receive display sink information indicating a space availability of a buffer of the display sink, the buffer to store at least a portion of the display information, and provide the display information to the display sink based on the display sink information. Other embodiments are described and claimed.

4. 发明申请

US20130262731A1 SUPERSPEED INTER-CHIP COMMUNICATIONS 有权
标题翻译：超级互通通信
公开(公告)号：US20130262731A1
公开(公告)日：2013-10-03
申请号：US13435926
申请日：2012-03-30
申请人： Sridharan Ranganathan , David J. Harriman , Anoop Mukker , Satheesh Chellappan , Karthi R. Vadivelu , Shalini Sharma , Zeeshan Sarwar
发明人： Sridharan Ranganathan , David J. Harriman , Anoop Mukker , Satheesh Chellappan , Karthi R. Vadivelu , Shalini Sharma , Zeeshan Sarwar
IPC分类号： G06F13/14
CPC分类号： G06F13/4291 , G06F13/4027 , G06F13/426 , Y02D10/14 , Y02D10/151
摘要： An interface for low power, high bandwidth communications between units in a device in provided herein. The interface comprises a USB 3.0 system interface and a SuperSpeed inter-chip (SSIC) protocol adaptor configured to facilitate communications between the USB 3.0 system interface and an M-PHY interface.
摘要翻译：用于本文提供的设备中的单元之间的低功率，高带宽通信的接口。接口包括USB 3.0系统接口和配置为便于USB 3.0系统接口和M-PHY接口之间的通信的SuperSpeed芯片间（SSIC）协议适配器。

5. 发明授权

US08347015B2 Power-optimized frame synchronization for multiple USB controllers with non-uniform frame rates 有权
标题翻译：针对具有不均匀帧速率的多个USB控制器进行功率优化的帧同步
公开(公告)号：US08347015B2
公开(公告)日：2013-01-01
申请号：US13305591
申请日：2011-11-28
申请人： Michael N. Derr , Darren L. Abramson , Bryan C. Doucette , Karthi R. Vadivelu
发明人： Michael N. Derr , Darren L. Abramson , Bryan C. Doucette , Karthi R. Vadivelu
IPC分类号： G06F13/14 , G06F3/00
CPC分类号： G06F1/3203 , G06F1/3253 , Y02D10/151 , Y02D50/20
摘要： A method, apparatus, and system to synchronize multiple host controllers with non-uniform frame rates. The apparatus includes a first host controller, a second host controller, and logic. The first host controller is configured to access memory at a first frame rate. The second host controller is configured to access the memory at a second frame rate which is different from the first frame rate. The logic is coupled to the first and second host controllers to synchronize the memory accesses of the first and second host controllers at a common frame rate. Other embodiments are described.
摘要翻译：一种以非均匀帧速率同步多个主机控制器的方法，装置和系统。该装置包括第一主机控制器，第二主机控制器和逻辑。第一主机控制器被配置为以第一帧速率访问存储器。第二主机控制器被配置为以与第一帧速率不同的第二帧速率访问存储器。该逻辑耦合到第一和第二主机控制器以以公共帧速率同步第一和第二主机控制器的存储器访问。描述其他实施例。

6. 发明授权

US06629001B1 Configurable controller for audio channels 失效
标题翻译：用于音频通道的可配置控制器
公开(公告)号：US06629001B1
公开(公告)日：2003-09-30
申请号：US09396979
申请日：1999-09-15
申请人： Karthi R. Vadivelu
发明人： Karthi R. Vadivelu
IPC分类号： G06F1700
CPC分类号： G06F3/16
摘要： The present invention is a method and apparatus to control audio channels. Configuration registers configure usage of the audio channels. A plurality of channel logic circuits are coupled to the corresponding configuration registers to provide logic functions to the audio channels according to the configured usage.
摘要翻译：本发明是一种控制音频通道的方法和装置。配置寄存器配置音频通道的使用。多个通道逻辑电路耦合到相应的配置寄存器，以根据配置的使用向音频通道提供逻辑功能。

7. 发明申请

US20190227753A1 System, Apparatus And Method For Sharing A Flash Device Among Multiple Masters Of A Computing Platform 审中-公开
公开(公告)号：US20190227753A1
公开(公告)日：2019-07-25
申请号：US16367608
申请日：2019-03-28
申请人： Zhenyu Zhu , Mikal Hunsaker , Karthi R. Vadivelu , Rahul Bhatt , Kenneth P. Foust , Rajesh Bhaskar , Amit Kumar Srivastava
发明人： Zhenyu Zhu , Mikal Hunsaker , Karthi R. Vadivelu , Rahul Bhatt , Kenneth P. Foust , Rajesh Bhaskar , Amit Kumar Srivastava
IPC分类号： G06F3/06 , G06F13/38 , G06F9/54
摘要： In one embodiment, a flash sharing controller is to enable a plurality of components of a platform to share a flash memory. The flash sharing controller may include: a flash sharing class layer including a configuration controller to configure the plurality of components to be flash master devices and configure a flash sharing slave device for the flash memory; and a physical layer coupled to the flash sharing class layer to communicate with the plurality of components via a bus. Other embodiments are described and claimed.

8. 发明授权

US08510583B2 Asynchronous sleep mode for host controller 有权
标题翻译：主机控制器的异步休眠模式
公开(公告)号：US08510583B2
公开(公告)日：2013-08-13
申请号：US12917795
申请日：2010-11-02
申请人： Choon Gun Por , Karthi R. Vadivelu
发明人： Choon Gun Por , Karthi R. Vadivelu
IPC分类号： G06F1/32
CPC分类号： G06F1/3203 , G06F1/3253 , G06F2213/0038 , Y02D10/151
摘要： Embodiments of the invention utilize a universal serial bus (USB) host controller to traverse an asynchronous data transfer list to identify data transfers to execute. The asynchronous data transfer list may include a plurality of header nodes, each header node to identify data transfers to one of a plurality of devices operatively coupled to an electronic device. The USB host controller may execute an extended sleep mode in response to identifying no data transfers to execute and receiving an indication that the system processor is in a sleep state. The USB host controller may exit the extended sleep mode in response to receiving an indication that the processor is in non-sleep state.
摘要翻译：本发明的实施例利用通用串行总线（USB）主机控制器来遍历异步数据传输列表以识别要执行的数据传输。异步数据传输列表可以包括多个报头节点，每个报头节点用于标识到可操作地耦合到电子设备的多个设备之一的数据传输。 USB主机控制器可以响应于不识别数据传输来执行扩展睡眠模式以执行并接收系统处理器处于睡眠状态的指示。响应于接收到处理器处于非睡眠状态的指示，USB主机控制器可以退出扩展睡眠模式。

9. 发明申请

US20120005508A1 ASYNCHRONOUS SLEEP MODE FOR HOST CONTROLLER 有权
标题翻译：主动控制器的异步休眠模式
公开(公告)号：US20120005508A1
公开(公告)日：2012-01-05
申请号：US12917795
申请日：2010-11-02
申请人： Choon Gun Por , Karthi R. Vadivelu
发明人： Choon Gun Por , Karthi R. Vadivelu
IPC分类号： G06F1/32
CPC分类号： G06F1/3203 , G06F1/3253 , G06F2213/0038 , Y02D10/151
摘要： Embodiments of the invention utilize a universal serial bus (USB) host controller to traverse an asynchronous data transfer list to identify data transfers to execute. The asynchronous data transfer list may include a plurality of header nodes, each header node to identify data transfers to one of a plurality of devices operatively coupled to an electronic device. The USB host controller may execute an extended sleep mode in response to identifying no data transfers to execute and receiving an indication that the system processor is in a sleep state. The USB host controller may exit the extended sleep mode in response to receiving an indication that the processor is in non-sleep state.
摘要翻译：本发明的实施例利用通用串行总线（USB）主机控制器来遍历异步数据传输列表以识别要执行的数据传输。异步数据传输列表可以包括多个报头节点，每个报头节点用于标识到可操作地耦合到电子设备的多个设备之一的数据传输。 USB主机控制器可以响应于不识别数据传输来执行扩展睡眠模式以执行并接收系统处理器处于睡眠状态的指示。响应于接收到处理器处于非睡眠状态的指示，USB主机控制器可以退出扩展睡眠模式。

10. 发明授权

US07076578B2 Race free data transfer algorithm using hardware based polling 失效
公开(公告)号：US07076578B2
公开(公告)日：2006-07-11
申请号：US09186056
申请日：2003-12-22
申请人： David I. Poisner , Karthi R. Vadivelu
发明人： David I. Poisner , Karthi R. Vadivelu
IPC分类号： G06F13/00
CPC分类号： G06F13/28
摘要： A method and apparatus for a race free data transfer algorithm using hardware based polling. One disclosed method transfers information between a target device and a buffer which is one of a set of buffers. The buffer is pointed to by a current buffer value stored in a controller. The current buffer value is adjusted to point to a next buffer if the current buffer value is different than a last buffer value. One of the set of buffers is serviced utilizing either the current buffer value or the last buffer value from the controller.

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