专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

WO2007146979A3 CIRCUIT CONFIGURATIONS HAVING FOUR TERMINAL JFET DEVICES 审中-公开
标题翻译：具有四个终端JFET器件的电路配置
公开(公告)号：WO2007146979A3
公开(公告)日：2008-06-19
申请号：PCT/US2007071075
申请日：2007-06-13
申请人： DSM SOLUTIONS INC , KAPOOR ASHOK KUMAR
发明人： KAPOOR ASHOK KUMAR
IPC分类号： H03K19/094 , H01L29/808
CPC分类号： H01L29/8086 , H01L29/785 , H01L2029/7857 , H01L2924/0002 , H03K19/09403 , H01L2924/00
摘要： Circuits using four terminal junction field effect transistors (JFETs) are disclosed. Such circuits can include various static and dynamic logic circuits, flip- flops, multiplexer, tri-state driver, phase detector, logic having variable speeds of operation, and/or analog circuit with such four terminal JFETs operating in a linear or nonlinear mode.
摘要翻译：公开了使用四端接点场效应晶体管（JFET）的电路。这样的电路可以包括各种静态和动态逻辑电路，触发器，多路复用器，三态驱动器，相位检测器，具有可变速度的逻辑，和/或具有以线性或非线性模式操作的这种四端JFET的模拟电路。

2. 发明申请

WO2007146979A2 CIRCUIT CONFIGURATIONS HAVING FOUR TERMINAL JFET DEVICES 审中-公开
标题翻译：具有四个终端JFET器件的电路配置
公开(公告)号：WO2007146979A2
公开(公告)日：2007-12-21
申请号：PCT/US2007/071075
申请日：2007-06-13
申请人： DSM SOLUTIONS, INC. , KAPOOR, Ashok, Kumar
发明人： KAPOOR, Ashok, Kumar
CPC分类号： H01L29/8086 , H01L29/785 , H01L2029/7857 , H01L2924/0002 , H03K19/09403 , H01L2924/00
摘要： Circuits using four terminal junction field effect transistors (JFETs) are disclosed. Such circuits can include various static and dynamic logic circuits, flip- flops, multiplexer, tri-state driver, phase detector, logic having variable speeds of operation, and/or analog circuit with such four terminal JFETs operating in a linear or nonlinear mode.
摘要翻译：公开了使用四端结场效应晶体管（JFET）的电路。这样的电路可以包括各种静态和动态逻辑电路，触发器，多路复用器，三态驱动器，相位检测器，具有可变速度的逻辑和/或具有以线性或非线性模式操作的这种四端JFET的模拟电路。

3. 发明申请

WO2007146872A2 SCALABLE PROCESS AND STRUCTURE FOR JFET FOR SMALL AND DECREASING LINE WIDTHS 审中-公开
标题翻译：用于小型和降低线宽度的JFET的可扩展过程和结构
公开(公告)号：WO2007146872A2
公开(公告)日：2007-12-21
申请号：PCT/US2007070864
申请日：2007-06-11
申请人： DSM SOLUTIONS INC , VORA MADHUKAR , KAPOOR ASHOK KUMAR
发明人： VORA MADHUKAR , KAPOOR ASHOK KUMAR
IPC分类号： H01L31/111 , H01L29/423 , H01L29/74 , H01L29/80
CPC分类号： H04L7/0337 , H01L21/2257 , H01L21/76816 , H01L21/76897 , H01L29/66901 , H01L29/808 , H01L2924/0002 , H03L7/0812 , H04L7/0037 , H01L2924/00
摘要： A scalable device structure and process for forming a normally off JFET with 45 NM linewidths or less. The contacts to the source, drain and gate areas are formed by forming a layer of oxide of a thickness of less than 1000 angstroms, and, preferably 500 angstroms or less on top of the substrate. A nitride layer is formed on top of the oxide layer and holes are etched for the source, drain and gate contacts. A layer of polysilicon is then deposited so as to fill the holes and the polysilicon is polished back to planarize it flush with the nitride layer. The polysilicon contacts are then implanted with the types of impurities necessary for the channel type of the desired transistor and the impurities are driven into the semiconductor substrate below to form source, drain and gate regions.
摘要翻译：用于形成45 N线宽以下的常闭JFET的可扩展器件结构和工艺。源极，漏极和栅极区域的触点通过在基板的顶部上形成厚度小于1000埃，优选为500埃或更小的氧化物层来形成。在氧化物层的顶部形成氮化物层，蚀刻用于源极，漏极和栅极接触的孔。然后沉积多晶硅层以填充孔，并且将多晶硅抛光回去以使其与氮化物层齐平。然后将多晶硅触点注入所需晶体管的沟道类型所需的杂质类型，并将杂质驱动到下面的半导体衬底中以形成源极，漏极和栅极区域。

4. 发明申请

WO2007146734A2 SELF ALIGNED GATE JFET STRUCTURE AND METHOD 审中-公开
标题翻译：自对准栅极晶体管结构和方法
公开(公告)号：WO2007146734A2
公开(公告)日：2007-12-21
申请号：PCT/US2007/070589
申请日：2007-06-07
申请人： DSM SOLUTIONS, INC. , KAPOOR, Ashok, Kumar
发明人： KAPOOR, Ashok, Kumar
IPC分类号： H01L31/112
CPC分类号： H01L29/808 , H01L29/1066 , H01L29/41775 , H01L29/66901
摘要： A JFET integrated onto a substrate having a semiconductor layer at least and having source and drain contacts over an active area and made of first polysilicon (or other conductors such as refractive metal or suicide) and a self-aligned gate contact made of second polysilicon which has been polished back to be flush with a top surface of a dielectric layer covering the tops of the source and drain contacts. The dielectric layer preferably has a nitride cap to act as a polish stop. In some embodiments, nitride covers the entire dielctric layer covering the source and drain contacts as well as the field oxide region defining an active area for said JFET. An embodiment with an epitaxially grown channel region formed on the surface of the substrate is also disclosed.
摘要翻译：集成在具有至少半导体层并且在有源区上具有源极和漏极接触并由第一多晶硅（或诸如折射金属或硅化物的其它导体）和由第二多晶硅制成的自对准栅极接触制成的基底的JFET，已经被抛光回与覆盖源极和漏极接触顶部的电介质层的顶表面齐平。电介质层优选具有用作抛光停止的氮化物盖。在一些实施例中，氮化物覆盖覆盖源极和漏极接触以及限定用于所述JFET的有源区域的场氧化物区域的整个电荷层。还公开了在衬底的表面上形成的外延生长沟道区的实施例。

5. 发明申请

WO2009006032A3 COMMON DATA LINE SIGNALING AND METHOD 审中-公开
标题翻译：常见的数据线信号和方法
公开(公告)号：WO2009006032A3
公开(公告)日：2009-02-26
申请号：PCT/US2008067446
申请日：2008-06-19
申请人： DSM SOLUTIONS INC , KAPOOR ASHOK KUMAR
发明人： KAPOOR ASHOK KUMAR
IPC分类号： H04L5/02 , G06F13/40
CPC分类号： G06F13/4004 , H04L27/12 , H04L27/148
摘要： A semiconductor device that includes transmitter circuits and receiver circuits that share a common data line and method is disclosed. Each transmitter circuit may include a frequency modulator that receives a stream of data and provides a frequency modulated data output at a predetermined carrier frequency. Each receiver may include a band pass filter that allows a corresponding frequency modulated data output from a corresponding transmitter circuit to pass through to a demodulator while essentially excluding the other frequency modulated data. In this way, a plurality of transmitter circuits can simultaneously transmit data with each one of the plurality of transmitter circuits transmitting data to a predetermined receiver circuit.
摘要翻译：公开了包括共享公共数据线和方法的发送器电路和接收器电路的半导体器件。每个发射机电路可以包括频率调制器，其接收数据流并且以预定的载波频率提供频率调制的数据输出。每个接收器可以包括带通滤波器，该带通滤波器允许从对应的发射器电路输出的相应的调频数据通过到解调器，同时基本排除其他调频数据。以这种方式，多个发送器电路可以将数据与多个发送器电路中的每一个发送数据同时发送到预定的接收器电路。

6. 发明申请

WO2008134148A1 JUNCTION FIELD EFFECT TRANSISTORS IN GERMANIUM AND SILICON-GERMANIUM ALLOYS AND METHOD FOR MAKING AND USING 审中-公开
标题翻译：锗和锗 - 锗合金中的结型场效应晶体管及其制造和使用方法
公开(公告)号：WO2008134148A1
公开(公告)日：2008-11-06
申请号：PCT/US2008/057945
申请日：2008-03-21
申请人： DSM SOLUTIONS, INC. , KAPOOR, Ashok Kumar , VORA, Madhukar B. , ZHANG, Weimin , SONKUSALE, Sachin R. , LIU, Yujie
发明人： KAPOOR, Ashok Kumar , VORA, Madhukar B. , ZHANG, Weimin , SONKUSALE, Sachin R. , LIU, Yujie
IPC分类号： H01L29/16 , H01L29/161 , H01L29/808 , H01L21/337 , H01L29/10 , H01L29/08 , H01L21/225 , H01L29/165 , H01L29/45 , H01L29/06 , H01L21/762 , H01L21/761
CPC分类号： H01L29/66901 , H01L21/2257 , H01L21/761 , H01L21/76224 , H01L29/0653 , H01L29/0843 , H01L29/1066 , H01L29/1075 , H01L29/16 , H01L29/161 , H01L29/165 , H01L29/45 , H01L29/808 , H01L29/8086
摘要： Junction field effect transistors (JFET) formed in substrates containing germanium. JFETs having polycrystalline semiconductor surface contacts (562, 530, 560, 532) with self-aligned suicide (580) formed thereon and self-aligned source, drain and gate regions (520, 522,540) formed by thermal drive-in of impurities from surface contacts into the substrate, and implanted link regions (522, 526). Others have a polycrystalline semiconductor gate surface contact and metal back gate, source and drain contacts and a metal surface contact to the gate surface contact with implanted source and drains and a self -aligned gate region. JFETs having a polycrystalline semiconductor gate surface contact and metal back gate, source and drain contacts and a metal surface contact to the- gate surface contact with implanted source and drains and a self-aligned gate region and suicide formed on the top of the source, drain and back gate contacts and on top of the gate polycrystalline semiconductor gate contact to which the metal surface contacts make electrical contact.
摘要翻译：在包含锗的衬底中形成的结型场效应晶体管（JFET）。具有在其上形成有自对准硅化物（580）的多晶半导体表面接触（562,530,560,532）的JFET，以及通过来自表面的杂质的热传导形成的自对准源极，漏极和栅极区域（520,522,540）接触到衬底中，以及植入的链接区域（522,526）。其他具有多晶半导体栅极表面接触和金属后栅极，源极和漏极接触以及与栅极表面接触的金属表面接触与注入源和漏极以及自对准栅极区域。具有多晶半导体栅极表面接触和金属背栅极，源极和漏极接触以及与栅极表面的金属表面接触的JFET与植入源和漏极接触，并且形成在源的顶部上的自对准栅极区域和硅化物，漏极和后栅极触点，并且在栅极多晶半导体栅极触点的顶部与金属表面接触形成电接触。

7. 发明申请

WO2009006032A2 COMMON DATA LINE SIGNALING AND METHOD 审中-公开
标题翻译：通用数据线信号和方法
公开(公告)号：WO2009006032A2
公开(公告)日：2009-01-08
申请号：PCT/US2008/067446
申请日：2008-06-19
申请人： DSM SOLUTIONS, INC. , KAPOOR, Ashok, Kumar
发明人： KAPOOR, Ashok, Kumar
IPC分类号： H04L5/02 , G06F13/40
CPC分类号： G06F13/4004 , H04L27/12 , H04L27/148
摘要： A semiconductor device that includes transmitter circuits and receiver circuits that share a common data line and method is disclosed. Each transmitter circuit may include a frequency modulator that receives a stream of data and provides a frequency modulated data output at a predetermined carrier frequency. Each receiver may include a band pass filter that allows a corresponding frequency modulated data output from a corresponding transmitter circuit to pass through to a demodulator while essentially excluding the other frequency modulated data. In this way, a plurality of transmitter circuits can simultaneously transmit data with each one of the plurality of transmitter circuits transmitting data to a predetermined receiver circuit.
摘要翻译：公开了一种包括共享公共数据线和方法的发射机电路和接收机电路的半导体器件。每个发射机电路可以包括接收数据流并且以预定载波频率提供频率调制数据输出的频率调制器。每个接收机可以包括带通滤波器，其允许从相应的发射机电路输出的对应的频率调制数据通过到解调器，同时基本排除其它调频数据。以这种方式，多个发射机电路可以同时将多个发射机电路中的每一个发送数据的数据发送到预定的接收机电路。

8. 发明申请

WO2007067684A3 METHOD OF PRODUCING AND OPERATING A LOW POWER JUNCTION FIELD EFFECT TRANSISTOR 审中-公开
标题翻译：低功率场效应晶体管的制造和运行方法
公开(公告)号：WO2007067684A3
公开(公告)日：2008-04-10
申请号：PCT/US2006046666
申请日：2006-12-07
申请人： DSM SOLUTIONS INC , KAPOOR ASHOK KUMAR
发明人： KAPOOR ASHOK KUMAR
IPC分类号： H03K19/0175
CPC分类号： H03K19/0941 , H01L27/098 , H01L29/66901 , H01L29/808 , H03K2217/0018
摘要： A method for using an inverter with a pair of complementary junction field effect transistors (CJFET) with a small linewidth is provided. The method includes having an input capacitance for said CJFET inverter to be less than the corresponding input capacitance of a CMOS inverter of similar linewidth. The CJFET operates at a power supply with a lesser value than the voltage drop across a forward-biased diode having a reduced switching power as compared to said CMOS inverter and having a propagation delay for said CJFET inverter that is at least comparable to the corresponding delay of said CMOS inverter.
摘要翻译：提供了一种使用具有小线宽的一对互补结场效应晶体管（CJFET）的逆变器的方法。该方法包括使所述CJFET反相器的输入电容小于类似线宽的CMOS反相器的对应输入电容。与所述CMOS反相器相比，CJFET工作在比具有降低的开关功率的正向偏置二极管的电压降低的电源，并且具有至少与相应延迟相当的所述CJFET反相器的传播延迟的CMOS反相器。

9. 发明申请

WO2007067684A2 METHOD OF PRODUCING AND OPERATING A LOW POWER JUNCTION FIELD EFFECT TRANSISTOR 审中-公开
标题翻译：低功率场效应晶体管的制造和运行方法
公开(公告)号：WO2007067684A2
公开(公告)日：2007-06-14
申请号：PCT/US2006/046666
申请日：2006-12-07
申请人： DSM SOLUTIONS, INC. , KAPOOR, Ashok, Kumar
发明人： KAPOOR, Ashok, Kumar
IPC分类号： H03K19/0175
CPC分类号： H03K19/0941 , H01L27/098 , H01L29/66901 , H01L29/808 , H03K2217/0018
摘要： A method for using an inverter with a pair of complementary junction field effect transistors (CJFET) with a small linewidth is provided. The method includes having an input capacitance for said CJFET inverter to be less than the corresponding input capacitance of a CMOS inverter of similar linewidth. The CJFET operates at a power supply with a lesser value than the voltage drop across a forward-biased diode having a reduced switching power as compared to said CMOS inverter and having a propagation delay for said CJFET inverter that is at least comparable to the corresponding delay of said CMOS inverter.
摘要翻译：提供了一种使用具有小线宽的一对互补结场效应晶体管（CJFET）的逆变器的方法。该方法包括使所述CJFET反相器的输入电容小于类似线宽的CMOS反相器的对应输入电容。与所述CMOS反相器相比，CJFET工作在比具有降低的开关功率的正向偏置二极管的电压降低的电源，并且具有至少与相应延迟相当的所述CJFET反相器的传播延迟的CMOS反相器。

10. 发明申请

WO2008042566A2 SEMICONDUCTOR DEVICE WITH CIRCUITS FORMED WITH ESSENTIALLY UNIFORM PATTERN DENSITY 审中-公开
标题翻译：具有基本形成均匀图形密度的电路的半导体器件
公开(公告)号：WO2008042566A2
公开(公告)日：2008-04-10
申请号：PCT/US2007/078216
申请日：2007-09-12
申请人： DSM SOLUTIONS, INC. , KAPOOR, Ashok, Kumar , CHOU, Richard, K. , THUMMALAPALLY, Damodar, R.
发明人： KAPOOR, Ashok, Kumar , CHOU, Richard, K. , THUMMALAPALLY, Damodar, R.
IPC分类号： H01L27/02 , H01L29/808 , H01L21/336 , H01L21/337 , H01L29/10
CPC分类号： H01L27/0207 , H01L29/1041 , H01L29/66901 , H01L29/78 , H01L29/808 , H01L29/8086 , H03K19/09403
摘要： A semiconductor device can include a first circuit section having at least one transistor coupled to at least three conductive lines formed from a conductive layer. No more than one of the at least one of the three conductive lines forms a control terminal of the at least one transistor. In addition, a second circuit section includes at least two transistors. Each such transistor can have a control terminal formed by a conductive line formed from the same conductive layer. The three conductive lines of the first circuit section can have the same pitch pattern as the conductive lines of the second circuit section.
摘要翻译：半导体器件可以包括具有至少一个晶体管的第一电路部分，耦合到由导电层形成的至少三个导电线。三条导线中的至少一条中的至少一条形成至少一个晶体管的控制端。此外，第二电路部分包括至少两个晶体管。每个这样的晶体管可以具有由由相同导电层形成的导电线形成的控制端子。第一电路部分的三根导线可以具有与第二电路部分的导线相同的间距图形。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式