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1. 发明授权

US5978930A Clock signal control system for stopping and activating a clock signal 失效
标题翻译：用于停止和激活时钟信号的时钟信号控制系统
公开(公告)号：US5978930A
公开(公告)日：1999-11-02
申请号：US946123
申请日：1997-10-07
申请人： Koichiro Furuta , Masayuki Mizuno , Junichi Goto
发明人： Koichiro Furuta , Masayuki Mizuno , Junichi Goto
IPC分类号： G06F15/16 , G06F1/04 , G06F1/10 , G06F15/177
CPC分类号： G06F1/10
摘要： A clock signal control system of the present invention includes a simple circuit for generating a clock stop signal. With this circuit, the system is small size and easy to design and consumes a minimum of power.
摘要翻译：本发明的时钟信号控制系统包括用于产生时钟停止信号的简单电路。使用该电路，该系统体积小巧易于设计，功耗最低。

2. 发明授权

US5446395A Test circuit for large scale integrated circuits on a wafer 失效
标题翻译：用于晶圆上大规模集成电路的测试电路
公开(公告)号：US5446395A
公开(公告)日：1995-08-29
申请号：US124071
申请日：1993-09-21
申请人： Junichi Goto
发明人： Junichi Goto
IPC分类号： G01R31/28 , G01R31/3185 , H01L21/66
CPC分类号： G01R31/318505 , G01R31/2884 , G01R31/318511
摘要： A test circuit for conducting a simultaneous test of a plurality of integrated circuits provided in dicing regions of a wafer. The test circuit has a pattern generator electrically connected to the integrated circuits through first interconnections for generating input signal patterns and subsequent transmission thereof to each of the integrated circuits and pattern compressor/comparator electrically connected to the integrated circuits through second interconnections for analyzing output signals fetched from the integrated circuits so as to conduct a simultaneous test of a plurality of the integrated circuits.
摘要翻译：一种测试电路，用于对设置在晶片切割区域中的多个集成电路进行同时测试。测试电路具有通过第一互连电连接到集成电路的模式发生器，用于产生输入信号模式，并随后通过第二互连电路连接到集成电路和图形压缩器/比较器，以分析输出信号从集成电路中进行多个集成电路的同时测试。

3. 发明申请

US20090097079A1 Image reading device, recording medium storing image reading program, image reading method and data signal 审中-公开
标题翻译：图像读取装置，存储图像读取程序的记录介质，图像读取方法和数据信号
公开(公告)号：US20090097079A1
公开(公告)日：2009-04-16
申请号：US12081816
申请日：2008-04-22
申请人： Hidetaka Hama , Kouji Yorimoto , Junichi Goto , Kenji Nomura , Kazuhiko Minowa
发明人： Hidetaka Hama , Kouji Yorimoto , Junichi Goto , Kenji Nomura , Kazuhiko Minowa
IPC分类号： H04N1/04
CPC分类号： H04N1/00795 , H04N1/00816 , H04N1/1013 , H04N1/193 , H04N2201/0081
摘要： An image reading device, which includes: an original document reading section that emits light to an original document and in the vicinity of the original document, receives reflected light and outputs image signals; an original document positioning guide that has at least a first color and a second color on a side receiving the light emitted from the original document reading section, and is used for settling a position of the original document; a detection section that monitors a first image signal in a scanning direction from the first color to the original document and a second image signal in a scanning direction from the second color to the original document, and detects a position for extracting image signals corresponding to the light reflected on the original document on the basis of a change occurring in either of the first image signal or the second image signal.
摘要翻译：一种图像读取装置，包括：原稿读取部，其对原稿发光，并在原稿附近，接收反射光并输出图像信号; 原稿定位引导件，其在接收从原始文档读取部分发射的光的一侧具有至少第一颜色和第二颜色，并且用于确定原始文档的位置; 检测部，其将从第一颜色到原稿的扫描方向的第一图像信号和从第二颜色向原稿的扫描方向上的第二图像信号进行监视，并且检测用于提取与第一颜色相对应的图像信号的位置基于在第一图像信号或第二图像信号中的任一个发生的变化在原始文档上反射的光。

4. 发明授权

US4675985A Method for manufacturing a semiconductor memory device having a high radiation resistance 失效
标题翻译：具有高耐辐射性的半导体存储器件的制造方法
公开(公告)号：US4675985A
公开(公告)日：1987-06-30
申请号：US568034
申请日：1984-01-04
申请人： Junichi Goto
发明人： Junichi Goto
IPC分类号： H01L21/52 , H01L21/58 , H01L23/556 , H01L27/10 , H01L23/28 , H01L23/30
CPC分类号： H01L24/83 , H01L23/556 , H01L24/33 , H01L2224/32225 , H01L2224/48091 , H01L2224/73265 , H01L2224/8319 , H01L2224/8385 , H01L24/48 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01018 , H01L2924/0102 , H01L2924/01027 , H01L2924/01033 , H01L2924/01039 , H01L2924/01082 , H01L2924/014 , H01L2924/07802 , H01L2924/15153 , H01L2924/15165 , H01L2924/19041 , H01L2924/30105 , H01L2924/3025 , Y10S438/918
摘要： In a method for manufacturing a semiconductor memory device, a semiconductor chip and an adhesive tape having an adhesive layer are prepared. The adhesive layer comprises a polyamic acid intermediate derived for example from a pyromellitic dianhydride and a diamine. The adhesive tape is pressed onto the semiconductor chip at a temperature of from about 250.degree. C. to about 400.degree. C. for a predetermined time period such as 2 to 5 sec.
摘要翻译：在制造半导体存储器件的方法中，制备了具有粘合剂层的半导体芯片和粘合带。粘合层包含衍生自例如均苯四酸二酐和二胺的聚酰胺酸中间体。将粘合带在约250℃至约400℃的温度下压制到半导体芯片上一段预定的时间，例如2至5秒。

5. 发明申请

US20120299930A1 DATA GENERATING METHOD 审中-公开
标题翻译：数据生成方法
公开(公告)号：US20120299930A1
公开(公告)日：2012-11-29
申请号：US13476585
申请日：2012-05-21
申请人： Junichi GOTO
发明人： Junichi GOTO
IPC分类号： G06T11/20 , G09G5/00
CPC分类号： G06T11/206
摘要： A data generating method includes: inputting parameter values to an input screen unit having an input box for inputting parameter values that prescribe the image data; and displaying the input parameter values on the auxiliary display screen unit for which the parameter values are displayed as two-dimensional shapes.
摘要翻译：一种数据生成方法，包括：向具有用于输入规定图像数据的参数值的输入框的输入画面单元输入参数值; 并且将显示参数值的辅助显示屏单元上的输入参数值显示为二维形状。

6. 发明授权

US07051314B2 Method of computer-assisted design of integrated circuit chips, and library of delay time values for computer-assisted design of such chips 失效
标题翻译：计算机辅助设计集成电路芯片的方法，以及这种芯片的计算机辅助设计的延迟时间值库
公开(公告)号：US07051314B2
公开(公告)日：2006-05-23
申请号：US10326379
申请日：2002-12-23
申请人： Junichi Goto
发明人： Junichi Goto
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G03F7/70425 , G06F17/5045 , G06F2217/12 , Y02P90/265
摘要： A method of placing integrated circuit chips on a wafer uses a library of average delay time values of logic gates. Exposure-dependent delay time values of the logic gates, which result from exposure of a unit area to a beam of radiation, are additionally stored in the library. These delay time values are detected by successively exposing unit areas of a test wafer to a beam of radiation as a function of relative positions of each integrated circuit chip within the unit exposure area. In a modified embodiment, only one integrated circuit chip within each unit area is exposed to the radiation beam, and the exposure-dependent delay time values are detected as a function of position within the exposed integrated circuit chip or as a function of distance from the center of the each unit area.
摘要翻译：将集成电路芯片放置在晶片上的方法使用逻辑门的平均延迟时间值的库。在图书馆中还附加存储由曝光单位区域到辐射束产生的逻辑门的曝光相关延迟时间值。这些延迟时间值是通过将测试晶片的单位面积依次暴露于单位曝光区域内的每个集成电路芯片的相对位置的函数来将辐射束连续曝光来检测的。在修改的实施例中，在每个单位区域内只有一个集成电路芯片暴露于辐射束，并且依赖于暴露的集成电路芯片中的曝光相关延迟时间值作为位置的函数被检测，或作为距离每个单位面积的中心。

7. 发明授权

US5328767A Resin composition and multi-layer structural material therefrom 失效
标题翻译：树脂组合物和多层结构材料
公开(公告)号：US5328767A
公开(公告)日：1994-07-12
申请号：US868654
申请日：1992-04-15
申请人： Yasuaki Miki , Shoji Takano , Junichi Goto , Takayuki Ota
发明人： Yasuaki Miki , Shoji Takano , Junichi Goto , Takayuki Ota
IPC分类号： B32B27/08 , B32B27/32 , C08L23/26 , C08L51/06 , C08L77/00 , C08L77/12 , B32B27/34 , B32B27/36
CPC分类号： C08L51/06 , C08L77/12 , Y10T428/31565 , Y10T428/31573 , Y10T428/31576 , Y10T428/31587
摘要： A resin composition comprising a polyester and a modified polyolefin, wherein said polyester has an amide bond in polymer main chain and said modified polyolefin has a carboxylic acid group or a derivative thereof.
摘要翻译：一种包含聚酯和改性聚烯烃的树脂组合物，其中所述聚酯在聚合物主链中具有酰胺键，所述改性聚烯烃具有羧酸基或其衍生物。

8. 发明授权

US5475828A Digital processor having plurality of memories and plurality of arithmetic logic units corresponding in number thereto and method for controlling the same 失效
标题翻译：数字处理器具有多个存储器和多个数量对应的算术逻辑单元及其控制方法
公开(公告)号：US5475828A
公开(公告)日：1995-12-12
申请号：US976924
申请日：1992-11-16
申请人： Junichi Goto
发明人： Junichi Goto
IPC分类号： G06F12/02 , G06F9/34 , G06F12/06 , G06T1/60
CPC分类号： G06F9/34 , G06T1/60
摘要： In a digital processor having a plurality of memories and a plurality of ALUs, each of address ports of each of the memories is associated with an address generation circuit capable of executing a loop processing required for address generation. With this arrangement, it is possible to access a plurality of memories, and therefore, the processing efficiency is improved.
摘要翻译：在具有多个存储器和多个ALU的数字处理器中，每个存储器的每个地址端口与能够执行地址产生所需的循环处理的地址产生电路相关联。通过这种布置，可以访问多个存储器，因此提高了处理效率。

9. 发明授权

US5410659A Digital processor with instruction memory of reduced storage size 失效
标题翻译：具有减少存储大小的指令存储器的数字处理器
公开(公告)号：US5410659A
公开(公告)日：1995-04-25
申请号：US47579
申请日：1993-04-13
申请人： Junichi Goto
发明人： Junichi Goto
IPC分类号： G06F9/22 , G06F9/30 , G06F9/38
CPC分类号： G06F9/3822 , G06F9/30145
摘要： A digital processor has a data processing unit having arithmetic/logic operation circuits, an instruction memory for storing an instruction word, and an instruction decoder for decoding the instruction word read from the instruction memory and outputting the control signals respectively to the arithmetic/logic operation circuits. Each instruction word has at least a first control field and a second control field. The instruction decoder has two decoding circuits. Each of the decoding circuits corresponds to each group of the arithmetic/logic operation circuits, receives the instruction word for decoding the second control field into a control signal and outputs an ENABLE signal. The ENABLE signal from the first decoding circuit is applied to the second decoding circuit, and the ENABLE signal from the second decoding circuit is applied to the first decoding circuit. Only one of the first and second decoding circuits outputs a control signal at a time.
摘要翻译：数字处理器具有具有算术/逻辑运算电路的数据处理单元，用于存储指令字的指令存储器和用于对从指令存储器读取的指令字进行解码的指令译码器，分别将控制信号输出到运算/逻辑运算电路。每个指令字具有至少第一控制字段和第二控制字段。指令译码器具有两个解码电路。每个解码电路对应于每组算术/逻辑运算电路，将用于将第二控制场解码的指令字接收到控制信号中，并输出ENABLE信号。来自第一解码电路的ENABLE信号被施加到第二解码电路，并且来自第二解码电路的ENABLE信号被施加到第一解码电路。第一和第二解码电路中只有一个一次输出控制信号。

10. 发明授权

US5221788A Polyurethane polyol and polyurethane coating composition employing said polyol 失效
标题翻译：聚氨酯聚氨酯和聚氨酯涂料组合物
公开(公告)号：US5221788A
公开(公告)日：1993-06-22
申请号：US940396
申请日：1992-09-03
申请人： Junichi Goto , Takayuki Ohta
发明人： Junichi Goto , Takayuki Ohta
IPC分类号： C08G18/10 , C08G18/32 , C08G18/38 , C08G18/64 , C08G18/75
CPC分类号： C08G18/755 , C08G18/10 , C08G18/3206 , C08G18/3831 , C08G18/6415
摘要： A polyurethane polyol obtained by reacting a hydrocarbon diol of the formula (A):HO--R--OH (A)wherein R is a C.sub.7-20 linear or branched alkylene group, with isophorone diisocyanate and having a number average molecular weight of from 500 to 20,000.

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