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    • 1. 发明申请
    • LEVEL TRANSITION DETERMINATION CIRCUIT AND METHOD FOR USING THE SAME
    • 水平过渡测定电路及其使用方法
    • US20120163794A1
    • 2012-06-28
    • US13191983
    • 2011-07-27
    • Jung Mao LINChing Yuan Yang
    • Jung Mao LINChing Yuan Yang
    • H04J14/00H03K5/00
    • H03K5/1534H04L7/0338
    • A level transition determination circuit includes a multi-phase clock generator, an oversampling unit, and a state detection circuit. The multi-phase clock generator is used for receiving an input clock signal and generating S×N clock signals, in which S and N are integers. Each clock signal is synchronized to the input clock signal and has a different delay time. The oversampling unit is used for performing N-times oversampling on M bit periods of the serial input data according to the clock signals, so as to generate M×N sampled values in parallel during the M bit periods. The state detection circuit is used for receiving (M×N)+1 sampled values and generating N detection signals by detecting level transitions between adjacent sampled values of the (M×N)+1 sampled values and the level transition results.
    • 电平转换确定电路包括多相时钟发生器,过采样单元和状态检测电路。 多相时钟发生器用于接收输入时钟信号并产生S×N个时钟信号,其中S和N是整数。 每个时钟信号与输入时钟信号同步并具有不同的延迟时间。 过采样单元用于根据时钟信号对串行输入数据的M位周期进行N次过采样,以便在M位周期期间并行生成M×N采样值。 状态检测电路用于通过检测(M×N)+1采样值的相邻采样值和电平转换结果之间的电平转换来接收(M×N)+1采样值并产生N个检测信号。
    • 4. 发明授权
    • Level transition determination circuit and method for using the same
    • 电平转换判定电路及其使用方法
    • US08615063B2
    • 2013-12-24
    • US13191983
    • 2011-07-27
    • Jung Mao LinChing Yuan Yang
    • Jung Mao LinChing Yuan Yang
    • H04L7/00
    • H03K5/1534H04L7/0338
    • A level transition determination circuit includes a multi-phase clock generator, an oversampling unit, and a state detection circuit. The multi-phase clock generator is used for receiving an input clock signal and generating S×N clock signals, in which S and N are integers. Each clock signal is synchronized to the input clock signal and has a different delay time. The oversampling unit is used for performing N-times oversampling on M bit periods of the serial input data according to the clock signals, so as to generate M×N sampled values in parallel during the M bit periods. The state detection circuit is used for receiving (M×N)+1 sampled values and generating N detection signals by detecting level transitions between adjacent sampled values of the (M×N)+1 sampled values and the level transition results.
    • 电平转换确定电路包括多相时钟发生器,过采样单元和状态检测电路。 多相时钟发生器用于接收输入时钟信号并产生S×N个时钟信号,其中S和N是整数。 每个时钟信号与输入时钟信号同步并具有不同的延迟时间。 过采样单元用于根据时钟信号对串行输入数据的M位周期进行N次过采样,以便在M位周期期间并行生成M×N采样值。 状态检测电路用于通过检测(M×N)+1采样值的相邻采样值和电平转换结果之间的电平转换来接收(M×N)+1采样值并产生N个检测信号。
    • 5. 发明申请
    • QUADRATURE VOLTAGE-CONTROLLED OSCILLATOR APPARATUS
    • 正弦电压控制振荡器装置
    • US20120154060A1
    • 2012-06-21
    • US13018378
    • 2011-01-31
    • Chih-Hsiang ChangJung-Mao LinChing-Yuan Yang
    • Chih-Hsiang ChangJung-Mao LinChing-Yuan Yang
    • H03B5/12
    • H03B5/1228H03B5/1212H03B5/1243H03B27/00
    • A quadrature voltage-controlled oscillator (QVCO) apparatus including a first VCO, a second VCO, a first energy-storage element, a second energy-storage element, a third energy-storage element and a fourth energy-storage element is provided. The first VCO has a first and a second phase output ends. The second VCO has a third and a fourth phase output ends. A first and a second ends of the first energy-storage element respectively connect to the first and the third phase output ends. A first and a second ends of the second energy-storage element respectively connect to the second and the third phase output ends. A first and a second ends of the third energy-storage element respectively connect to the second and the fourth phase output ends. A first and a second ends of the fourth energy-storage element respectively connect to the first and the fourth phase output ends.
    • 提供了包括第一VCO,第二VCO,第一能量存储元件,第二能量存储元件,第三能量存储元件和第四能量存储元件的正交压控振荡器(QVCO)装置。 第一个VCO具有第一和第二相输出端。 第二个VCO具有第三和第四相输出端。 第一能量存储元件的第一端和第二端分别连接到第一和第三相输出端。 第二能量存储元件的第一端和第二端分别连接到第二和第三相输出端。 第三储能元件的第一和第二端分别连接到第二和第四相输出端。 第四能量存储元件的第一和第二端分别连接到第一和第四相输出端。
    • 8. 发明申请
    • BUST-MODE CLOCK AND DATA RECOVERY CIRCUIT USING PHASE SELECTING TECHNOLOGY
    • 使用相位选择技术的BUST模式时钟和数据恢复电路
    • US20100040182A1
    • 2010-02-18
    • US12266530
    • 2008-11-06
    • Ching-Yuan YangJung-Mao LinYu-Min Lin
    • Ching-Yuan YangJung-Mao LinYu-Min Lin
    • H04L7/00
    • H04L7/0337H03L7/0814H03L7/091H04L7/0041H04L7/0087H04Q11/0067H04Q2011/0079
    • A bust-mode clock and data recovery circuit using phase selecting technology is provided. In the data recovery circuit, a phase-locked loop (PLL) circuit is used for providing a plurality of fixed clock signals, each of which has a clock phase. An oversampling phase selecting circuit is coupled to the phase-locked loop circuit and used for detecting a data edge of a received data signal by using the clock signals and selects a clock phase to be locked according to the location of the data edge. A delay-locked loop (DLL) circuit is coupled to the phase-locked loop circuit and the oversampling phase selecting circuit, and used for comparing the data phase of the data signal with the clock phase of the selected clock signal, so as to delay the data phase of the data signal by a delay time until the data phase is locked as the clock phase.
    • 提供了采用相位选择技术的突发模式时钟和数据恢复电路。 在数据恢复电路中,使用锁相环(PLL)电路来提供多个具有时钟相位的固定时钟信号。 过采样相位选择电路耦合到锁相环电路,用于通过使用时钟信号检测接收数据信号的数据沿,并根据数据沿的位置选择要锁定的时钟相位。 延迟锁定回路(DLL)电路耦合到锁相环电路和过采样相位选择电路,并用于将数据信号的数据相位与所选择的时钟信号的时钟相位进行比较,以便延迟 数据信号的数据相位延迟一个延迟时间,直到数据相位被锁定为时钟相位。
    • 9. 发明授权
    • Random access method, parameter assignment method, wireless communication device, and base station using the same
    • 随机存取方法,参数分配方法,无线通信装置以及使用该方法的基站
    • US08588163B2
    • 2013-11-19
    • US13196911
    • 2011-08-03
    • Jung-Mao LinChie-Ming Chou
    • Jung-Mao LinChie-Ming Chou
    • H04W4/00
    • H04W74/085H04W48/02
    • A random access method, a parameter assignment method, a wireless communication device, and a base station using the same are provided. The random access method is adapted for the wireless communication device to perform a random access process with the base station, and includes following steps. The wireless communication device transmits a preamble code to the base station, obtains an indicator in a packet transmitted from the base station, and determines whether to obtain a first random access response and a second random access response according to the indicator. When the transmission of the preamble code by the wireless communication device encounters a collision and the indicator is set the wireless communication device performs a random access process by using the command in the first random access response. Otherwise, the wireless communication device performs the conventional process.
    • 提供了一种随机存取方法,参数分配方法,无线通信装置和使用该方法的基站。 随机接入方法适用于无线通信设备与基站进行随机接入过程,并且包括以下步骤。 无线通信装置向基站发送前导码,获取从基站发送的分组中的指示符,并根据该指标确定是否获得第一随机接入响应和第二随机接入响应。 当由无线通信设备发送前导码遇到冲突时,无线通信设备通过使用第一随机接入响应中的命令来执行随机接入过程。 否则,无线通信装置执行常规处理。