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1. 发明授权

US07504309B2 Pre-silicide spacer removal 失效
标题翻译：预硅化物间隔物去除
公开(公告)号：US07504309B2
公开(公告)日：2009-03-17
申请号：US11548842
申请日：2006-10-12
申请人： Thomas W. Dyer , Sunfei Fang , Jiang Yan , Jun Jung Kim , Yaocheng Liu , Huilong Zhu
发明人： Thomas W. Dyer , Sunfei Fang , Jiang Yan , Jun Jung Kim , Yaocheng Liu , Huilong Zhu
IPC分类号： H01L21/336
CPC分类号： H01L29/665 , H01L21/32 , H01L29/6653 , H01L29/66545 , H01L29/6659
摘要： A method forms a gate conductor over a substrate, and simultaneously forms spacers on sides of the gate conductor and a gate cap on the top of the gate conductor. Isolation regions are formed in the substrate and the method implants an impurity into exposed regions of the substrate not protected by the gate conductor and the spacers to form source and drain regions. The method deposits a mask over the gate conductor, the spacers, and the source and drain regions. The mask is recessed to a level below a top of the gate conductor but above the source and drain regions, such that the spacers are exposed and the source and drain regions are protected by the mask. With the mask in place, the method then safely removes the spacers and the gate cap, without damaging the source/drain regions or the isolation regions (which are protected by the mask). Next, the method removes the mask and then forms silicide regions on the gate conductor and the source and drain regions.
摘要翻译：一种方法在衬底上形成栅极导体，同时在栅极导体的侧面和栅极导体的顶部上形成栅极盖。在衬底中形成隔离区域，并且该方法将杂质注入未被栅极导体和间隔物保护的衬底的暴露区域中以形成源区和漏区。该方法在栅极导体，间隔物以及源极和漏极区域上沉积掩模。掩模凹陷到栅极导体的顶部下方但在源极和漏极区域之上的水平面，使得间隔物被暴露，并且源极和漏极区域被掩模保护。在掩模就位的情况下，该方法然后安全地去除间隔物和栅极盖，而不损坏源极/漏极区域或隔离区域（被掩模保护）。接下来，该方法移除掩模，然后在栅极导体和源极和漏极区域上形成硅化物区域。

2. 发明申请

US20080220584A1 Methods of Forming Integrated Circuit Structures Using Insulator Deposition and Insulator Gap Filling Techniques 有权
标题翻译：使用绝缘体沉积和绝缘子间隙填充技术形成集成电路结构的方法
公开(公告)号：US20080220584A1
公开(公告)日：2008-09-11
申请号：US11683590
申请日：2007-03-08
申请人： Jun-jung Kim , Ja-hum Ku , Jae-eon Park , Sunfei Fang , Alois Gutmann , O-sung Kwon , Johnny Widodo , Dae-won Yang
发明人： Jun-jung Kim , Ja-hum Ku , Jae-eon Park , Sunfei Fang , Alois Gutmann , O-sung Kwon , Johnny Widodo , Dae-won Yang
IPC分类号： H01L29/82
CPC分类号： H01L21/0217 , C23C16/56 , H01L21/02211 , H01L21/02266 , H01L21/02274 , H01L21/31051 , H01L21/3185 , H01L21/76826 , H01L21/76829 , H01L21/76837 , H01L21/823425
摘要： Methods of forming integrated circuit devices include depositing an electrically insulating layer onto an integrated circuit substrate having integrated circuit structures thereon. This deposition step results in the formation of an electrically insulating layer having an undulating surface profile, which includes at least one peak and at least on valley adjacent to the at least one peak. A non-uniform thickening step is then performed. This non-uniform thickening step includes thickening a portion of the electrically insulating layer by redepositing portions of the electrically insulating layer from the least one peak to the at least one valley. This redeposition occurs using a sputter deposition technique that utilizes the electrically insulating layer as a sputter target.
摘要翻译：形成集成电路器件的方法包括在其上具有集成电路结构的集成电路衬底上沉积电绝缘层。该沉积步骤导致形成具有起伏表面轮廓的电绝缘层，该电绝缘层包括至少一个峰和至少与至少一个峰相邻的峰。然后进行非均匀的增稠步骤。这种不均匀的增厚步骤包括通过将电绝缘层的部分从至少一个峰重新沉积到至少一个谷部来增厚电绝缘层的一部分。使用利用电绝缘层作为溅射靶的溅射沉积技术发生这种再沉积。

3. 发明申请

US20080173934A1 INTEGRATED CIRCUIT SYSTEM EMPLOYING STRESS-ENGINEERED SPACERS 有权
标题翻译：集成电路系统应用于工程应用的空间
公开(公告)号：US20080173934A1
公开(公告)日：2008-07-24
申请号：US12048994
申请日：2008-03-14
申请人： Jae Gon Lee , Jong Ho Yang , Victor Chan , Jun Jung Kim
发明人： Jae Gon Lee , Jong Ho Yang , Victor Chan , Jun Jung Kim
IPC分类号： H01L27/092
CPC分类号： H01L29/7833 , H01L21/823807 , H01L21/823864 , H01L27/0629 , H01L27/092 , H01L29/165 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/7843 , H01L29/7848
摘要： An integrated circuit system that includes: providing a substrate including a first region with a first device and a second device and a second region with a resistance device; configuring the first device, the second device, and the resistance device to include a first spacer and a second spacer; forming a stress inducing layer over the first region and the second region; processing at least a portion of the stress inducing layer formed over the first region to alter the stress within the stress inducing layer; and forming a third spacer adjacent the second spacer of the first device and the second device from the stress inducing layer.
摘要翻译：一种集成电路系统，包括：提供包括具有第一装置的第一区域的基板和具有电阻装置的第二区域; 配置第一装置，第二装置和电阻装置以包括第一间隔件和第二间隔件; 在所述第一区域和所述第二区域上形成应力诱导层; 处理形成在第一区域上的应力诱导层的至少一部分，以改变应力诱导层内的应力; 以及从所述应力诱导层形成邻近所述第一器件和所述第二器件的第二间隔物的第三间隔物。

4. 发明授权

US07297584B2 Methods of fabricating semiconductor devices having a dual stress liner 有权
标题翻译：制造具有双重应力衬垫的半导体器件的方法
公开(公告)号：US07297584B2
公开(公告)日：2007-11-20
申请号：US11246471
申请日：2005-10-07
申请人： Jae-Eon Park , Ja-Hum Ku , Jun-Jung Kim , Dae-Kwon Kang , Young Way Teh
发明人： Jae-Eon Park , Ja-Hum Ku , Jun-Jung Kim , Dae-Kwon Kang , Young Way Teh
IPC分类号： H01L21/8234 , H01L21/8238 , H01L21/336
CPC分类号： H01L21/823807 , H01L21/0217 , H01L21/02274 , H01L21/268 , H01L21/3185 , H01L21/823814 , H01L21/823835 , H01L21/823864 , H01L29/7843
摘要： In a semiconductor device having a dual stress liner for improving electron mobility, the dual stress liner includes a first liner portion formed on a PMOSFET and a second liner portion formed on an NMOSFET. The first liner portion has a first compressive stress, and the second liner portion has a second compressive stress smaller than the first compressive stress. The dual stress liner may be formed by forming a stress liner on a semiconductor substrate on which the PMOSFET and the NMOSFET are formed and selectively exposing a portion of the stress liner on the NMOSFET.
摘要翻译：在具有用于改善电子迁移率的双应力衬垫的半导体器件中，双应力衬垫包括形成在PMOSFET上的第一衬垫部分和形成在NMOSFET上的第二衬垫部分。第一衬里部分具有第一压缩应力，并且第二衬套部分具有小于第一压缩应力的第二压缩应力。双应力衬垫可以通过在其上形成PMOSFET和NMOSFET的半导体衬底上形成应力衬垫而形成，并且选择性地暴露在NMOSFET上的应力衬垫的一部分。

5. 发明申请

US20160343660A1 WIRING STRUCTURES AND SEMICONDUCTOR DEVICES 审中-公开
标题翻译：接线结构和半导体器件
公开(公告)号：US20160343660A1
公开(公告)日：2016-11-24
申请号：US15073640
申请日：2016-03-17
申请人： Jun-Jung KIM , Young-Bae KIM , Jong-Sam KIM , Jin-Hyeung PARK , Jeong-Hoon AHN , Hyeok-Sang OH , Kyoung-Woo LEE , Hyo-Seon LEE , Suk-Hee JANG
发明人： Jun-Jung KIM , Young-Bae KIM , Jong-Sam KIM , Jin-Hyeung PARK , Jeong-Hoon AHN , Hyeok-Sang OH , Kyoung-Woo LEE , Hyo-Seon LEE , Suk-Hee JANG
IPC分类号： H01L23/535 , H01L23/528 , H01L23/522 , H01L27/088
CPC分类号： H01L23/5226 , H01L21/76802 , H01L21/76807 , H01L21/76832 , H01L21/76834 , H01L21/76873 , H01L21/76882 , H01L21/823475 , H01L23/485 , H01L23/53295 , H01L27/088
摘要： A wiring structure includes a substrate, a lower insulation layer on the substrate, a lower wiring in the lower insulation layer, a first etch-stop layer covering the lower wiring and including a metallic dielectric material, a second etch-stop layer on the first etch-stop layer and the lower insulation layer, an insulating interlayer on the second etch-stop layer, and a conductive pattern extending through the insulating interlayer, the second etch-stop layer and the first etch-stop layer and electrically connected to the lower wiring.
摘要翻译：布线结构包括衬底，衬底上的下绝缘层，下绝缘层中的下布线，覆盖下布线并包括金属电介质材料的第一蚀刻停止层，第一蚀刻停止层蚀刻停止层和下绝缘层，在第二蚀刻停止层上的绝缘中间层，以及延伸穿过绝缘中间层，第二蚀刻停止层和第一蚀刻停止层并电连接到下部绝缘层的导电图案接线。

6. 发明授权

US08338245B2 Integrated circuit system employing stress-engineered spacers 有权
标题翻译：采用应力工程间隔件的集成电路系统
公开(公告)号：US08338245B2
公开(公告)日：2012-12-25
申请号：US12048994
申请日：2008-03-14
申请人： Jae Gon Lee , Jong Ho Yang , Victor Chan , Jun Jung Kim
发明人： Jae Gon Lee , Jong Ho Yang , Victor Chan , Jun Jung Kim
IPC分类号： H01L21/8238
CPC分类号： H01L29/7833 , H01L21/823807 , H01L21/823864 , H01L27/0629 , H01L27/092 , H01L29/165 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/7843 , H01L29/7848
摘要： An integrated circuit system that includes: providing a substrate including a first region with a first device and a second device and a second region with a resistance device; configuring the first device, the second device, and the resistance device to include a first spacer and a second spacer; forming a stress inducing layer over the first region and the second region; processing at least a portion of the stress inducing layer formed over the first region to alter the stress within the stress inducing layer; and forming a third spacer adjacent the second spacer of the first device and the second device from the stress inducing layer.
摘要翻译：一种集成电路系统，包括：提供包括具有第一装置的第一区域的基板和具有电阻装置的第二区域; 配置第一装置，第二装置和电阻装置以包括第一间隔件和第二间隔件; 在所述第一区域和所述第二区域上形成应力诱导层; 处理形成在第一区域上的应力诱导层的至少一部分，以改变应力诱导层内的应力; 以及从所述应力诱导层形成邻近所述第一器件和所述第二器件的第二间隔物的第三间隔物。

7. 发明申请

US20110156110A1 Field Effect Transistors Having Gate Electrode Silicide Layers with Reduced Surface Damage 审中-公开
标题翻译：具有栅电极的场效应晶体管具有降低的表面损伤的硅化物层
公开(公告)号：US20110156110A1
公开(公告)日：2011-06-30
申请号：US13043059
申请日：2011-03-08
申请人： Jun-jung Kim , Sang-jine Park , Min-ho Lee , Thomas W. Dyer , Sunfei Fang , O-sung Kwon , Johnny Widodo
发明人： Jun-jung Kim , Sang-jine Park , Min-ho Lee , Thomas W. Dyer , Sunfei Fang , O-sung Kwon , Johnny Widodo
IPC分类号： H01L29/772
CPC分类号： H01L29/7833 , H01L29/665 , H01L29/6653 , H01L29/7843
摘要： Methods of forming integrated circuit devices include forming a field effect transistor having a gate electrode, a sacrificial spacer on a sidewall of the gate electrode and silicided source/drain regions. The sacrificial spacer is used as an implantation mask when forming highly doped portions of the source/drain regions. The sacrificial spacer is then removed from the sidewall of the gate electrode. A stress-inducing electrically insulating layer, which is configured to induce a net tensile stress (for NMOS transistors) or compressive stress (for PMOS transistors) in a channel region of the field effect transistor, is then formed on the sidewall of the gate electrode.
摘要翻译：形成集成电路器件的方法包括形成具有栅电极的场效应晶体管，栅电极的侧壁上的牺牲隔离物和硅化源/漏区。当形成源极/漏极区域的高掺杂部分时，牺牲间隔物用作注入掩模。然后从栅电极的侧壁去除牺牲隔离物。然后，在栅电极的侧壁上形成应力诱导电绝缘层，其被配置为在场效应晶体管的沟道区域中引起净拉伸应力（用于NMOS晶体管）或压应力（用于PMOS晶体管）。

8. 发明授权

US07790622B2 Methods for removing gate sidewall spacers in CMOS semiconductor fabrication processes 有权
标题翻译：在CMOS半导体制造工艺中去除栅极侧壁间隔物的方法
公开(公告)号：US07790622B2
公开(公告)日：2010-09-07
申请号：US11778038
申请日：2007-07-14
申请人： Kyoung Woo Lee , Ja Hum Ku , Jun Jung Kim , Chong Kwang Chang , Min-Chul Sun , Jong Ho Yang , Thomas W. Dyer
发明人： Kyoung Woo Lee , Ja Hum Ku , Jun Jung Kim , Chong Kwang Chang , Min-Chul Sun , Jong Ho Yang , Thomas W. Dyer
IPC分类号： H01L21/311
CPC分类号： H01L21/31144 , H01L21/823814 , H01L21/823835 , H01L21/823864
摘要： Semiconductor fabrication processes are provided for removing sidewall spacers from gate structures while mitigating or otherwise preventing defect mechanisms such as damage to metal silicide structures or otherwise impeding or placing limitations on subsequent process flows.
摘要翻译：提供半导体制造工艺用于从门结构去除侧壁间隔物，同时减轻或以其他方式预防诸如损坏金属硅化物结构的缺陷机制或以其它方式阻碍或限制后续工艺流程。

9. 发明授权

US07612414B2 Overlapped stressed liners for improved contacts 失效
标题翻译：重叠的应力衬垫改善了接触
公开(公告)号：US07612414B2
公开(公告)日：2009-11-03
申请号：US11693254
申请日：2007-03-29
申请人： Xiangdong Chen , Jun Jung Kim , Young Gun Ko , Jae-Eun Park , Haining S. Yang
发明人： Xiangdong Chen , Jun Jung Kim , Young Gun Ko , Jae-Eun Park , Haining S. Yang
IPC分类号： H01L21/8238 , H01L23/18
CPC分类号： H01L21/0217 , H01L21/02274 , H01L21/3185 , H01L21/823807 , H01L29/7843
摘要： A semiconductor structure is provided which includes a first semiconductor device in a first active semiconductor region and a second semiconductor device in a second active semiconductor region. A first dielectric liner overlies the first semiconductor device and a second dielectric liner overlies the second semiconductor device, with the second dielectric liner overlapping the first dielectric liner at an overlap region. The second dielectric liner has a first portion having a first thickness contacting an apex of the second gate conductor and a second portion extending from peripheral edges of the second gate conductor which has a second thickness substantially greater than the first thickness. A first conductive via contacts at least one of the first or second gate conductors and the conductive via extends through the first and second dielectric liners at the overlap region. A second conductive via may contact at least one of a source region or a drain region of the second semiconductor device.
摘要翻译：提供一种半导体结构，其包括第一有源半导体区域中的第一半导体器件和第二有源半导体区域中的第二半导体器件。第一电介质衬垫覆盖在第一半导体器件上，并且第二电介质衬垫覆盖在第二半导体器件上，第二电介质衬垫在重叠区域与第一电介质衬垫重叠。第二电介质衬垫具有第一部分，第一部分具有与第二栅极导体的顶点接触的第一厚度和从第二栅极导体的周边边延伸的第二部分，第二部分具有基本上大于第一厚度的第二厚度。第一导电通孔接触第一或第二栅极导体和导电通孔中的至少一个延伸穿过第一和第二电介质衬垫在重叠区域。第二导电通孔可以接触第二半导体器件的源极区域或漏极区域中的至少一个。

10. 发明申请

US20090014807A1 DUAL STRESS LINERS FOR INTEGRATED CIRCUITS 审中-公开
标题翻译：用于集成电路的双应力线
公开(公告)号：US20090014807A1
公开(公告)日：2009-01-15
申请号：US11777290
申请日：2007-07-13
申请人： Teck Jung TANG , Dae Kwon Kang , Sunfei Fang , Tae Hoon Lee , Scott D. Allen , Fang Chen , Frank Huebinger , Jun Jung Kim , Jae Eun Park
发明人： Teck Jung TANG , Dae Kwon Kang , Sunfei Fang , Tae Hoon Lee , Scott D. Allen , Fang Chen , Frank Huebinger , Jun Jung Kim , Jae Eun Park
IPC分类号： H01L29/94 , H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823871 , H01L21/823878 , H01L29/665 , H01L29/7843
摘要： Dual stress liners for CMOS applications are provided. The dual stress liners can be formed from silicon nitride having a first portion for inducing a first stress and a second portion for inducing a second stress. An interface between the first and second stress portions is self-aligned and co-planar. To produce a co-planar self-aligned interface, polishing, for example, mechanical chemical polishing is used.
摘要翻译：提供用于CMOS应用的双重应力衬垫。双重应力衬垫可以由具有用于诱发第一应力的第一部分的氮化硅和用于引起第二应力的第二部分形成。第一和第二应力部分之间的界面是自对准的并且是共面的。为了产生共面自对准界面，使用例如机械化学抛光进行抛光。

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