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1. 发明授权

US07568141B2 Method and apparatus for testing embedded cores 有权
标题翻译：嵌入式核心测试方法和装置
公开(公告)号：US07568141B2
公开(公告)日：2009-07-28
申请号：US11963689
申请日：2007-12-21
申请人： Sankaran M. Menon , Luis A. Basto , Tien Dinh , Thomas Tomazin , Juan G. Revilla
发明人： Sankaran M. Menon , Luis A. Basto , Tien Dinh , Thomas Tomazin , Juan G. Revilla
IPC分类号： G01R31/28
CPC分类号： G11C29/48 , G01R31/318508 , G01R31/318513 , G01R31/318541 , G01R31/318555 , G11C2029/0401 , G11C2029/3202
摘要： The inputs to an embedded core, e.g., the core terminals, may not be directly connected to pins on the SoC. The lack of direct access to an embedded core's terminals may complicate testing of the embedded core. A test wrapper including boundary scan test (BST) cells may be used to test an embedded core. Dual function BST/ATPG (Automatic Test Pattern Generation) cells may be used to perform both BST and ATPG tests on embedded cores.
摘要翻译：嵌入式核心（例如核心终端）的输入可能不直接连接到SoC上的引脚。直接访问嵌入式核心终端的可能会使嵌入式核心的测试复杂化。可以使用包括边界扫描测试（BST）单元的测试包装器来测试嵌入式核心。双功能BST / ATPG（自动测试模式生成）单元可用于对嵌入式核心执行BST和ATPG测试。

2. 发明授权

US07028129B2 Method and apparatus for converting an external memory access into a local memory access in a processor core 失效
公开(公告)号：US07028129B2
公开(公告)日：2006-04-11
申请号：US10040904
申请日：2001-12-28
申请人： Juan G. Revilla , Minh D. Tran
发明人： Juan G. Revilla , Minh D. Tran
IPC分类号： G06F13/00
CPC分类号： G06F12/06
摘要： A processor may include a processor core, which interprets and executes instructions, and a system bus interface, which enables the processor to communicate with a system. The system bus interface may include a fill bus and a DMA bus. The system bus interface may include a bridge between the fill bus and the DMA bus which enables the system bus interface to re-route information placed on the fill bus onto the DMA bus and back into the core.

3. 发明授权

US06920515B2 Early exception detection 有权
标题翻译：早期异常检测
公开(公告)号：US06920515B2
公开(公告)日：2005-07-19
申请号：US09823095
申请日：2001-03-29
申请人： Juan G. Revilla , Ravi P. Singh , Charles P. Roth
发明人： Juan G. Revilla , Ravi P. Singh , Charles P. Roth
IPC分类号： G06F9/00 , G06F9/30 , G06F9/38 , G06F11/30 , G06F13/24
CPC分类号： G06F9/3865 , G06F9/30149 , G06F9/3816 , G06F9/3836
摘要： A programmable processor is adapted to detect exception conditions associated with one or more instructions before the instructions are executed. The detected exception conditions may be stored with the one or more instructions in a prefetch unit. Then, the exception conditions may be issued in parallel with the issuance of the instructions.
摘要翻译：可编程处理器适于在执行指令之前检测与一个或多个指令相关联的异常情况。检测到的异常条件可以与预取单元中的一个或多个指令一起存储。然后，异常条件可以与发布指令并行发布。

4. 发明授权

US06874078B2 Merged control/process element processor for executing VLIW simplex instructions with SISD control/SIMD process mode bit 失效
标题翻译：用于使用SISD控制/ SIMD过程模式位执行VLIW单工指令的合并控制/处理元件处理器
公开(公告)号：US06874078B2
公开(公告)日：2005-03-29
申请号：US10620144
申请日：2003-07-15
申请人： Gerald G. Pechanek , Juan G. Revilla
发明人： Gerald G. Pechanek , Juan G. Revilla
IPC分类号： G06F15/16 , G06F9/30 , G06F9/318 , G06F15/173 , G06F15/80 , G06F9/40
CPC分类号： G06F9/3885 , G06F9/3012 , G06F9/30145 , G06F9/30189 , G06F9/3887 , G06F15/17343 , G06F15/8007
摘要： A highly parallel data processing system includes an array of n processing elements (PEs) and a controller sequence processor (SP) wherein at least one PE is combined with the controller SP to create a Dynamic Merged Processor (DP) which supports two modes of operation. In its first mode of operation, the DP acts as one of the PEs in the array and participates in the execution of single-instruction-multiple-data (SIMD) instructions. In the second mode of operation, the DP acts as the controlling element for the array of PEs and executes non-array instructions. To support these two modes of operation, the DP includes a plurality of execution units and two general-purpose register files. The execution units are “shared” in that they can execute instructions in either mode of operation. With very long instruction word (VLIW) capability, both modes of operation can be in effect on a cycle by cycle basis for every VLIW executed. This structure allows the controlling element in a highly parallel SIMD processor to be reused as one of the processing elements in the array to reduce the overall number of transistors and wires in the SIMD processor while maintaining its capabilities and performance.
摘要翻译：高度并行的数据处理系统包括n个处理元件（PE）和控制器序列处理器（SP）的阵列，其中至少一个PE与控制器SP组合以创建支持两种操作模式的动态合并处理器（DP）。在其第一种操作模式中，DP充当阵列中的PE之一，并参与执行单指令多数据（SIMD）指令。在第二种操作模式中，DP充当PE阵列的控制元件，并执行非阵列指令。为了支持这两种操作模式，DP包括多个执行单元和两个通用寄存器文件。执行单元是“共享的”，因为它们可以在任一操作模式下执行指令。具有非常长的指令字（VLIW）能力，两种操作模式可以在执行的每个VLIW的基础上逐周期生效。这种结构允许高度并行的SIMD处理器中的控制元件被重新用作阵列中的处理元件之一，以在保持其能力和性能的同时减少SIMD处理器中的晶体管和导线的总数。

5. 发明授权

US5561614A Method and apparatus for testing pin isolation for an integrated circuit in a low power mode of operation 失效
标题翻译：用于在低功耗工作模式下测试集成电路的引脚隔离的方法和装置
公开(公告)号：US5561614A
公开(公告)日：1996-10-01
申请号：US380893
申请日：1995-01-30
申请人： Juan G. Revilla , Alfred L. Crouch
发明人： Juan G. Revilla , Alfred L. Crouch
IPC分类号： G06F11/273 , G05B23/02
CPC分类号： G06F11/2733
摘要： A low power mode of an integrated circuit (IC) 10 is tested via a test controller 50. The IC 10 is placed in a low power mode where a plurality of pins represented by the pins 82, 72, and 62 are isolated from the internal circuitry, such as CPU 30, via circuits 60, 70, and 80. It is difficult, if not impossible, to test the IC 10 when in a low power mode since all pins are isolated from external circuitry and all clocks are stopped. Therefore, in order to test the low power mode, the test controller 50 can be selectively taken-out of low power mode via a RESET IN signal while all other circuitry in the IC 10 remains in the isolated low power mode. Test controller 50 can then conduct logical low power internal testing of the IC 10 while it is in low power mode and isolated. This testing in done by communicating data via the DATA IN and DATA OUT pins in a serial scan chain manner.
摘要翻译：通过测试控制器50测试集成电路（IC）10的低功率模式.IC 10被置于低功率模式，其中由引脚82,72和62表示的多个引脚与内部电路，例如CPU30，经由电路60,70和80.由于所有引脚与外部电路隔离并且所有时钟停止，所以在低功率模式下测试IC 10是困难的，甚至是不可能的。因此，为了测试低功率模式，测试控制器50可以经由RESET IN信号被选择性地从低功率模式中取出，同时IC 10中的所有其它电路保持在隔离的低功率模式。然后，测试控制器50可以在IC 10处于低功率模式并隔离时进行IC 10的逻辑低功耗内部测试。通过数据输入和数据输出引脚以串行扫描链方式传送数据完成此测试。

6. 发明授权

US07313739B2 Method and apparatus for testing embedded cores 有权
标题翻译：嵌入式核心测试方法和装置
公开(公告)号：US07313739B2
公开(公告)日：2007-12-25
申请号：US10335149
申请日：2002-12-31
申请人： Sankaran M. Menon , Luis A. Basto , Tien Dinh , Thomas Tomazin , Juan G. Revilla
发明人： Sankaran M. Menon , Luis A. Basto , Tien Dinh , Thomas Tomazin , Juan G. Revilla
IPC分类号： G11C29/00
CPC分类号： G11C29/48 , G01R31/318508 , G01R31/318513 , G01R31/318541 , G01R31/318555 , G11C2029/0401 , G11C2029/3202
摘要： Testing memory devices. An apparatus may include a test module operative to perform a test on a plurality of pipelined memory elements and a fail trace module operative to interrupt the test in response to identifying a failure of a memory element and to store an address of said memory element in a storage unit.
摘要翻译：测试存储设备。装置可以包括可操作以对多个流水线存储器元件执行测试的测试模块和响应于识别存储器元件的故障并且将所述存储器元件的地址存储在存储器元件中的操作来中断测试的故障跟踪模块存储单元。

7. 发明授权

US07124285B2 Peak power reduction when updating future file 有权
标题翻译：更新未来文件时峰值功耗降低
公开(公告)号：US07124285B2
公开(公告)日：2006-10-17
申请号：US09823276
申请日：2001-03-29
申请人： Ryo Inoue , Juan G. Revilla
发明人： Ryo Inoue , Juan G. Revilla
IPC分类号： G06F15/00
CPC分类号： G06F9/3836 , G06F9/3857 , G06F9/3863
摘要： In one implementation, a programmable processor is adapted to include a first set of registers and a second set of registers. The first set of registers may have a future file, and the second set of registers may be architectural registers. Following a termination of an instruction in the processor, the future file may be restored with values in the second set of registers. The future file is restored over more than one clock cycle.
摘要翻译：在一个实现中，可编程处理器适于包括第一组寄存器和第二组寄存器。第一组寄存器可能有一个未来的文件，第二组寄存器可以是架构寄存器。在处理器中的指令终止之后，可以使用第二组寄存器中的值来恢复将来的文件。未来文件将在多个时钟周期内恢复。

8. 发明授权

US5623636A Data processing system and method for providing memory access protection using transparent translation registers and default attribute bits 失效
标题翻译：使用透明翻译寄存器和默认属性位提供存储器访问保护的数据处理系统和方法
公开(公告)号：US5623636A
公开(公告)日：1997-04-22
申请号：US149496
申请日：1993-11-09
申请人： Juan G. Revilla , Art Parmet
发明人： Juan G. Revilla , Art Parmet
IPC分类号： G06F12/02 , G06F12/14 , G06F12/08
CPC分类号： G06F12/1441
摘要： A data processing system (10 or 28) and method uses a memory management unit (MMU 14). The processor has two privileged modes of operations, such as a user mode and a supervisor mode of operation. The MMU 14 has a first mode of operation wherein logical address translation is performed via cache accesses and tablewalks, and a second mode of operation. The second mode of operation involves providing translation attribute bits from one of either a first transparent translation register (TTR 16), a second transparent translation register (TTR 18), or a default location (22). The TTRs (16 and 18) can each map different address spaces and different addressed memory sizes and the default location (22) covers all memory that is not mapped by one of the TTRs (16 or 18). The default location (22) is programmable, provides write protection, and provides attribute bits independent from the privilege mode.
摘要翻译：数据处理系统（10或28）和方法使用存储器管理单元（MMU 14）。处理器具有两种特权操作模式，例如用户模式和主管操作模式。 MMU 14具有第一操作模式，其中通过高速缓存访问和行进行进行逻辑地址转换，以及第二操作模式。第二操作模式涉及从第一透明转换寄存器（TTR 16），第二透明转换寄存器（TTR18）或默认位置（22）之一提供转换属性位。 TTR（16和18）可以各自映射不同的地址空间和不同的寻址存储器大小，并且默认位置（22）覆盖未被TTR之一（16或18）映射的所有存储器。默认位置（22）是可编程的，提供写保护，并提供与特权模式无关的属性位。

9. 发明授权

US07272705B2 Early exception detection 有权
标题翻译：早期异常检测
公开(公告)号：US07272705B2
公开(公告)日：2007-09-18
申请号：US11135862
申请日：2005-05-23
申请人： Juan G. Revilla , Ravi P. Singh , Charles P. Roth
发明人： Juan G. Revilla , Ravi P. Singh , Charles P. Roth
IPC分类号： G06F11/00
CPC分类号： G06F9/3865 , G06F9/30149 , G06F9/3816 , G06F9/3836
摘要： A programmable processor is adapted to detect exception conditions associated with one or more instructions before the instructions are executed. The detected exception conditions may be stored with the one or more instructions in a prefetch unit. Then, the exception conditions may be issued in parallel with the issuance of the instructions.
摘要翻译：可编程处理器适于在执行指令之前检测与一个或多个指令相关联的异常情况。检测到的异常条件可以与预取单元中的一个或多个指令一起存储。然后，异常条件可以与发布指令并行发布。

10. 发明授权

US06219776B1 Merged array controller and processing element 有权
标题翻译：合并阵列控制器和处理元件
公开(公告)号：US06219776B1
公开(公告)日：2001-04-17
申请号：US09169072
申请日：1998-10-09
申请人： Gerald G. Pechanek , Juan G. Revilla
发明人： Gerald G. Pechanek , Juan G. Revilla
IPC分类号： G06F1300
CPC分类号： G06F9/3885 , G06F9/3012 , G06F9/30145 , G06F9/30189 , G06F9/3887 , G06F15/17343 , G06F15/8007
摘要： A highly parallel data processing system includes an array of n processing elements (PEs) and a controller sequence processor (SP) wherein at least one PE is combined with the controller SP to create a Dynamic Merged Processor (DP) which supports two modes of operation. In its first mode of operation, the DP acts as one of the PEs in the array and participates in the execution of single-instruction-multiple-data (SIMD) instructions. In the second mode of operation, the DP acts as the controlling element for the array of PEs and executes non-array instructions. To support these two modes of operation, the DP includes a plurality of execution units and two general-purpose register files. The execution units are “shared” in that they can execute instructions in either mode of operation. With very long instruction word (VLIW) capability, both modes of operation can be in effect on a cycle by cycle basis for every VLIW executed. This structure allows the controlling element in a highly parallel SIMD processor to be reused as one of the processing elements in the array to reduce the overall number of transistors and wires in the SIMD processor while maintaining its capabilities and performance.
摘要翻译：高度并行的数据处理系统包括n个处理元件（PE）和控制器序列处理器（SP）的阵列，其中至少一个PE与控制器SP组合以创建支持两种操作模式的动态合并处理器（DP）。在其第一种操作模式中，DP充当阵列中的PE之一，并参与执行单指令多数据（SIMD）指令。在第二种操作模式中，DP充当PE阵列的控制元件，并执行非阵列指令。为了支持这两种操作模式，DP包括多个执行单元和两个通用寄存器文件。执行单元是“共享的”，因为它们可以在任一操作模式下执行指令。具有非常长的指令字（VLIW）能力，两种操作模式可以在执行的每个VLIW的基础上逐周期生效。这种结构允许高度并行的SIMD处理器中的控制元件被重新用作阵列中的处理元件之一，以在保持其能力和性能的同时减少SIMD处理器中的晶体管和导线的总数。

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