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1. 发明授权

US5777928A Multi-port register 失效
标题翻译：多端口寄存器
公开(公告)号：US5777928A
公开(公告)日：1998-07-07
申请号：US785575
申请日：1997-01-21
申请人： Rohit A. Vidwans , Wesley D. McCullough , Joel Huang , Joseph F. Rohlman
发明人： Rohit A. Vidwans , Wesley D. McCullough , Joel Huang , Joseph F. Rohlman
IPC分类号： G06F9/30 , G06F9/318 , G06F9/38 , G11C8/16 , G11C7/00
CPC分类号： G06F9/30141 , G06F9/3017 , G06F9/384 , G06F9/3885 , G11C8/16
摘要： A multi-port register contains a plurality of cells each capable of storing at least two states. The cells contain at least one read and one write port. Each read port contains a corresponding read enable line, a read data line, and a read transistor stack. Each write port contains a corresponding write enable line, write data line, and a write transistor stack. The read data line is coupled to a pre-charge circuit that charges the read data line to a pre-determined threshold level prior to reading the contents of the cell. The read transistor stack couples the output of the cell to the corresponding read data line such that the read data line is pulled to ground when the cell stores a first logic state, and the read data line retains the pre-determined voltage state when the cell stores the second logic state. The write transistor stack couples the write data line to the cell such that writing a first logic state on the write data line pulls the input to the cell to a low logic state, and writing a second logic state on the write data line drives the input to the cell to a high logic state. The multi-port register has application for use in a superscalar microprocessor performing out-of-order dispatch and execution and speculative execution.
摘要翻译：多端口寄存器包含多个能够存储至少两个状态的单元。单元格至少包含一个读写端口。每个读取端口包含对应的读使能线，读数据线和读晶体管堆。每个写入端口包含相应的写入使能线，写入数据线和写入晶体管堆叠。读取数据线耦合到在读取单元的内容之前将读取数据线充电到预定阈值级别的预充电电路。读取晶体管堆叠将单元的输出耦合到对应的读取数据线，使得当单元存储第一逻辑状态时，读取的数据线被拉到地，并且读取的数据线保持预定的电压状态，当单元存储第二个逻辑状态。写晶体管堆叠将写数据线耦合到单元，使得在写数据线上写入第一逻辑状态将单元的输入拉到低逻辑状态，并且在写数据线上写入第二逻辑状态驱动输入到单元到高逻辑状态。多端口寄存器具有用于执行无序调度和执行和推测执行的超标量微处理器的应用。

2. 发明授权

US5787454A Recorder buffer with interleaving mechanism for accessing a multi-parted circular memory array 失效
标题翻译：重新排序缓冲区，具有用于访问多端口循环存储器阵列的交织机制
公开(公告)号：US5787454A
公开(公告)日：1998-07-28
申请号：US578964
申请日：1995-12-27
申请人： Joseph F. Rohlman
发明人： Joseph F. Rohlman
IPC分类号： G06F7/78 , G11C7/10 , G11C8/16 , G06F12/02 , G06F13/16 , G11C8/00
CPC分类号： G06F7/785 , G11C7/1042 , G11C8/16
摘要： A buffer comprises a memory array, a write circuit and a read circuit. The memory array comprises one or more memory banks. Each of the memory banks is made up of a plurality of memory cells. Each memory cell has one read port and one write port. The write circuit stores a first variable number of data items to the one or more memory banks by utilizing the one write port of a portion of the memory cells. The read circuit reads a second variable number of data outputs from the one or more memory banks by utilizing the one read port of a portion of the memory cells. At least of portion of the plurality of memory cells may include one or more additional write ports which are not used for writing the first variable number of data inputs to the one or more memory banks, and at least of portion of the plurality of memory cells may include one or more additional read ports which are not used for reading the second variable number of data outputs from the one or more memory banks. Additionally, the memory array comprises one or more write bitlines that share discontinuous metal tracks with one or more read bitlines.
摘要翻译：缓冲器包括存储器阵列，写入电路和读取电路。存储器阵列包括一个或多个存储体。每个存储体由多个存储单元构成。每个存储单元都有一个读端口和一个写端口。写入电路通过利用存储器单元的一部分的一个写入端口将第一可变数量的数据项存储到一个或多个存储体。读取电路通过利用存储器单元的一部分的一个读取端口从一个或多个存储体读取第二可变数量的数据输出。多个存储器单元的至少一部分可以包括一个或多个附加写入端口，其不用于将第一可变数量的数据输入写入到一个或多个存储体，并且多个存储器单元的至少一部分可以包括不用于从一个或多个存储体读取第二可变数量的数据输出的一个或多个附加读端口。此外，存储器阵列包括一个或多个写入位线，其共享具有一个或多个读取位线的不连续的金属轨道。

3. 发明授权

US5574935A Superscalar processor with a multi-port reorder buffer 失效
标题翻译：超标量处理器带有多端口重排序缓冲器
公开(公告)号：US5574935A
公开(公告)日：1996-11-12
申请号：US346078
申请日：1994-11-29
申请人： Rohit A. Vidwans , Wesley D. McCullough , Joel Huang , Joseph F. Rohlman
发明人： Rohit A. Vidwans , Wesley D. McCullough , Joel Huang , Joseph F. Rohlman
IPC分类号： G06F9/30 , G06F9/318 , G06F9/38 , G11C8/16 , G06F12/00
CPC分类号： G06F9/30141 , G06F9/3017 , G06F9/384 , G06F9/3885 , G11C8/16
摘要： A multi-port register contains a plurality of cells each capable of storing at least two states. The cells contain at least one read and one write port. Each read port contains a corresponding read enable line, a read data line, and a read transistor stack. Each write port contains a corresponding write enable line, write data line, and a write transistor stack. The read data line is coupled to a pre-charge circuit that charges the read data line to a predetermined threshold level prior to reading the contents of the cell. The read transistor stack couples the output of the cell to the corresponding read data line such that the read data line is pulled to ground when the cell stores a first logic state, and the read data line retains the pre-determined voltage state when the cell stores the second logic state. The write transistor stack couples the write data line to the cell such that writing a first logic state on the write data line pulls the input to the cell to a low logic state, and writing a second logic state on the write data line drives the input to the cell to a high logic state. The multi-port register has application for use in a superscalar microprocessor performing out-of-order dispatch and execution and speculative execution.
摘要翻译：多端口寄存器包含多个能够存储至少两个状态的单元。单元格至少包含一个读写端口。每个读取端口包含对应的读使能线，读数据线和读晶体管堆。每个写入端口包含相应的写入使能线，写入数据线和写入晶体管堆叠。读取数据线耦合到在读取单元的内容之前将读取数据线充电到预定阈值电平的预充电电路。读取晶体管堆叠将单元的输出耦合到对应的读取数据线，使得当单元存储第一逻辑状态时，读取的数据线被拉到地，并且读取的数据线保持预定的电压状态，当单元存储第二个逻辑状态。写晶体管堆叠将写数据线耦合到单元，使得在写数据线上写入第一逻辑状态将单元的输入拉到低逻辑状态，并且在写数据线上写入第二逻辑状态驱动输入到单元到高逻辑状态。多端口寄存器具有用于执行无序调度和执行和推测执行的超标量微处理器的应用。

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