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1. 发明授权

US08872545B2 Exclusive OR circuit 有权
标题翻译：异或电路
公开(公告)号：US08872545B2
公开(公告)日：2014-10-28
申请号：US13604548
申请日：2012-09-05
申请人： Joong Ho Lee
发明人： Joong Ho Lee
IPC分类号： H03K19/21
CPC分类号： H03K19/21
摘要： An exclusive OR circuit includes, inter alia: a low pass unit configured to apply a second data to an output node when a first data is at a low level and to apply the first data to the output node when the second data is at a low level, and a discharge unit configured to discharge a voltage level of the output node when the first and second data are at a high level.
摘要翻译：异或电路尤其包括：低通单元，被配置为当第一数据处于低电平时将第二数据应用于输出节点，并且当第二数据处于低电平时将第一数据应用于输出节点以及放电单元，被配置为当第一和第二数据处于高电平时放电输出节点的电压电平。

2. 发明申请

US20140232637A1 HEAD MOUNTED DISPLAY APPARATUS AND CONTENTS DISPLAY METHOD 有权
标题翻译：头安装显示装置和内容显示方法
公开(公告)号：US20140232637A1
公开(公告)日：2014-08-21
申请号：US14131762
申请日：2012-07-06
申请人： Ji Hyung Park , Dong Wook Yoon , Yong Hun Choi , Joong Ho Lee
发明人： Ji Hyung Park , Dong Wook Yoon , Yong Hun Choi , Joong Ho Lee
IPC分类号： G02B27/01 , G06T19/00 , G06F3/01
CPC分类号： G02B27/017 , G02B2027/014 , G02B2027/0178 , G02B2027/0187 , G06F3/012 , G06F3/017 , G06T19/006
摘要： Disclosed are a head-mounted display apparatus and a contents display method. The head-mounted display apparatus includes: a mobile device tracing information processing unit for receiving position information or orientation information of a mobile device and generating tracing information of the mobile device based on the received position information or orientation information of the mobile device; a gesture processing unit for receiving input information of the mobile device and generating gesture information to change an output format of contents by using the received input information; a rendering unit for generating a predetermined virtually augmented contents image based on the tracing information of the mobile device and the gesture information; and a display unit for displaying the generated virtually augmented contents image.
摘要翻译：公开了一种头戴式显示装置和内容显示方法。头戴式显示装置包括：移动装置跟踪信息处理单元，用于接收移动装置的位置信息或取向信息，并基于所接收的移动装置的位置信息或取向信息，生成移动装置的跟踪信息; 手势处理单元，用于接收所述移动装置的输入信息，并且通过使用所接收的输入信息来产生用于改变内容的输出格式的手势信息; 渲染单元，用于基于所述移动设备的跟踪信息和所述手势信息来生成预定的虚拟增强内容图像; 以及显示单元，用于显示生成的虚拟增强内容图像。

3. 发明申请

US20100290296A1 SEMICONDUCTOR MEMORY DEVICE 失效
标题翻译：半导体存储器件
公开(公告)号：US20100290296A1
公开(公告)日：2010-11-18
申请号：US12490690
申请日：2009-06-24
申请人： Joong-Ho Lee
发明人： Joong-Ho Lee
IPC分类号： G11C29/00
CPC分类号： G11C29/838 , G11C29/24 , G11C29/816
摘要： A semiconductor memory device includes a plurality of memory cell matrixes each of which contains plural memory cell arrays whose number is lager than 2n and smaller than 2n+1, n being a natural number. The semiconductor memory device includes normal memory cell arrays including 2m numbers of memory cell arrays of the plurality of memory cell matrixes, m being a bit of addresses, wherein a data access operation is performed on normal memory cells in the normal memory cell arrays as normal word lines corresponding to the normal memory cells are activated in response to the addresses, and additional redundancy memory cell arrays in the plurality of memory cell matrixes, wherein repair-expected memory cells in the normal memory cell arrays are replaced with the additional redundancy memory cell arrays as redundancy word lines corresponding to the additional redundancy memory cells are activated in response to the addresses corresponding to the repair-expected memory cells.
摘要翻译：半导体存储器件包括多个存储单元矩阵，每个存储单元矩阵包含多于2n并且小于2n + 1的多个存储单元阵列，n是自然数。半导体存储器件包括包括多个存储单元矩阵的2m个存储单元阵列的正常存储单元阵列，m是地址位，其中在正常存储单元阵列中的正常存储单元上执行数据访问操作，如正常对应于正常存储器单元的字线响应于地址被激活，并且多个存储单元矩阵中的附加冗余存储单元阵列，其中正常存储器单元阵列中的修复预期存储单元被替换为附加冗余存储单元对应于附加冗余存储单元的冗余字线的阵列响应于对应于修复预期存储单元的地址被激活。

4. 发明申请

US20100202222A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20100202222A1
公开(公告)日：2010-08-12
申请号：US12494844
申请日：2009-06-30
申请人： Joong-Ho Lee
发明人： Joong-Ho Lee
IPC分类号： G11C7/10 , G11C7/02
CPC分类号： G11C11/4097 , G11C7/02 , G11C7/1066 , G11C7/18 , G11C2207/005
摘要： A semiconductor memory device includes first and second sub-memory-cell areas configured to form a memory cell matrix and include a first bit line and a second bit line respectively to form a data transfer path corresponding to a predetermined memory cell, an additional bit line configured to cross the first sub-memory-cell area and form a data transfer path by being connected with the second bit line and a sensing and amplifying unit configured to sense and amplify data inputted through the additional bit line and the first bit line.
摘要翻译：半导体存储器件包括被配置为形成存储单元矩阵并且分别包括第一位线和第二位线的第一和第二子存储器单元区域，以形成对应于预定存储器单元的数据传输路径，附加位线被配置为跨越第一子存储单元区域并通过与第二位线连接形成数据传送路径;感测和放大单元，被配置为感测和放大通过附加位线和第一位线输入的数据。

5. 发明申请

US20090147614A1 SEMICONDUCTOR MEMORY APPARATUS 有权
标题翻译：半导体存储器
公开(公告)号：US20090147614A1
公开(公告)日：2009-06-11
申请号：US12170262
申请日：2008-07-09
申请人： Joong-Ho Lee
发明人： Joong-Ho Lee
IPC分类号： G11C8/00
CPC分类号： G11C11/4097 , G11C7/02 , G11C7/08 , G11C7/12 , G11C7/18 , G11C11/4091 , G11C11/4094
摘要： A semiconductor memory includes a cell mat configured to include a plurality of memory cells to which a first bit line pair or a second bit line pair is connected; a sense amplifier configured to amplify a positive sensing line and a negative sensing line in response to a first bit line equalize signal; a column selecting unit configured to connect the positive sensing line and the negative sensing line to a first data bus and a second data bus, respectively, in response to a column selection signal; and a share control unit configured to connect the positive sensing line and a positive first bit line of the first bit line pair or a positive second bit line of the second bit line pair in response to a second bit line equalize signal, a positive share control signal and a negative share control signal.
摘要翻译：半导体存储器包括被配置为包括连接第一位线对或第二位线对的多个存储单元的单元阵列; 感测放大器，被配置为响应于第一位线均衡信号放大正感测线路和负感测线路; 列选择单元，被配置为分别响应于列选择信号将正感测线和负感测线连接到第一数据总线和第二数据总线; 以及共享控制单元，被配置为响应于第二位线均衡信号，连接第一位线对的正感测线和正的第一位线或第二位线对的正的第二位线，正共享控制信号和负共享控制信号。

6. 发明申请

US20130265082A1 EXCLUSIVE OR CIRCUIT 有权
标题翻译：独家或电路
公开(公告)号：US20130265082A1
公开(公告)日：2013-10-10
申请号：US13604548
申请日：2012-09-05
申请人： Joong Ho LEE
发明人： Joong Ho LEE
IPC分类号： H03K19/21
CPC分类号： H03K19/21
摘要： An exclusive OR circuit includes, inter alia: a low pass unit configured to apply a second data to an output node when a first data is at a low level and to apply the first data to the output node when the second data is at a low level, and a discharge unit configured to discharge a voltage level of the output node when the first and second data are at a high level.
摘要翻译：异或电路尤其包括：低通单元，被配置为当第一数据处于低电平时将第二数据应用于输出节点，并且当第二数据处于低电平时将第一数据应用于输出节点以及放电单元，被配置为当第一和第二数据处于高电平时放电输出节点的电压电平。

7. 发明授权

US08504903B2 Data error check circuit, data error check method, data transmission method using data error check function, semiconductor memory apparatus and memory system using data error check function 失效
标题翻译：数据错误检查电路，数据错误检查方法，使用数据错误检查功能的数据传输方法，使用数据错误检查功能的半导体存储器和存储器系统
公开(公告)号：US08504903B2
公开(公告)日：2013-08-06
申请号：US12970869
申请日：2010-12-16
申请人： Joong Ho Lee
发明人： Joong Ho Lee
IPC分类号： H03M13/00
CPC分类号： G06F11/1004 , G11C2029/0411
摘要： Various embodiments of a memory system are disclosed. In one exemplary embodiment, the memory system may include a semiconductor memory apparatus configured to generate error check signals in a column direction and a row direction of data groups to be transmitted through a plurality of data input/output terminals in a read operation and output the error check signals together with the data groups, and a memory controller configured to control data read/write operations of the semiconductor memory apparatus, generate error check signals by performing error check in a column direction and a row direction of data groups to be transmitted in a write operation, and provide the error check signals to the semiconductor memory apparatus together with the data groups.
摘要翻译：公开了存储器系统的各种实施例。在一个示例性实施例中，存储器系统可以包括：半导体存储器装置，被配置为在读操作中通过多个数据输入/输出端发送数据组的列方向和行方向的错误校验信号，并输出错误检查信号与数据组一起，以及存储器控制器，被配置为控制半导体存储器件的数据读/写操作，通过在要发送的数据组的列方向和行方向上执行错误校验来生成错误校验信号写操作，并且与数据组一起向半导体存储装置提供错误检查信号。

8. 发明授权

US08279698B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US08279698B2
公开(公告)日：2012-10-02
申请号：US13285445
申请日：2011-10-31
申请人： Joong-Ho Lee
发明人： Joong-Ho Lee
IPC分类号： G17C7/02
CPC分类号： G11C11/4097 , G11C7/02 , G11C7/1066 , G11C7/18 , G11C2207/005
摘要： A semiconductor memory device includes first and second sub-memory-cell areas configured to form a memory cell matrix and include a first bit line and a second bit line respectively to form a data transfer path corresponding to a predetermined memory cell, an additional bit line configured to cross the first sub-memory-cell area and form a data transfer path by being connected with the second bit line and a sensing and amplifying unit configured to sense and amplify data inputted through the additional bit line and the first bit line.
摘要翻译：半导体存储器件包括被配置为形成存储单元矩阵并且分别包括第一位线和第二位线的第一和第二子存储器单元区域，以形成对应于预定存储器单元的数据传输路径，附加位线被配置为跨越第一子存储单元区域并通过与第二位线连接形成数据传送路径;感测和放大单元，被配置为感测和放大通过附加位线和第一位线输入的数据。

9. 发明授权

US07934047B2 Memory module and memory system 有权
标题翻译：内存模块和内存系统
公开(公告)号：US07934047B2
公开(公告)日：2011-04-26
申请号：US12013845
申请日：2008-01-14
申请人： Joong-Ho Lee
发明人： Joong-Ho Lee
IPC分类号： G06F13/00 , G06F13/28
CPC分类号： G11C5/02
摘要： A memory module includes a plurality of ranks that each include a first pin group and a second pin group for receiving external pin signals, and a rank selecting unit included in each of the plurality of ranks, the rank selecting unit configured to output different rank pin signals to each rank by using signals of the first pin group.
摘要翻译：存储器模块包括多个排列，每个排列包括用于接收外部引脚信号的第一引脚组和第二引脚组，以及包括在多个等级的每一个中的等级选择单元，所述等级选择单元被配置为输出不同的等级引脚通过使用第一引脚组的信号将信号发送到每个等级。

10. 发明申请

US20090128635A1 APPARATUS AND METHOD FOR RUNNING DUAL CAMERAS IN A PORTABLE TERMINAL 有权
标题翻译：在便携式终端中运行双摄像机的装置和方法
公开(公告)号：US20090128635A1
公开(公告)日：2009-05-21
申请号：US12274648
申请日：2008-11-20
申请人： Il-Seob BAEK , Seung-Jun LEE , Joong-Ho LEE
发明人： Il-Seob BAEK , Seung-Jun LEE , Joong-Ho LEE
IPC分类号： H04N5/225
CPC分类号： H04N5/232
摘要： An apparatus and method for separating and connecting a main camera and a sub camera in a portable terminal are provided. The portable terminal includes a main camera for receiving a main clock signal from a main chip and transmitting a main camera pixel clock signal to the main chip in response to the main clock signal, a sub camera for receiving the main clock signal from the main chip and transmitting a sub camera pixel clock signal to the main chip in response to the main clock signal, and a switch for configuring a path from the main chip to at least one of the main camera and the sub camera.
摘要翻译：提供了一种用于在便携式终端中分离和连接主摄像机和子摄像机的装置和方法。便携式终端包括用于从主芯片接收主时钟信号并且响应于主时钟信号将主相机像素时钟信号发送到主芯片的主相机，用于从主芯片接收主时钟信号的副相机以及响应于所述主时钟信号将副相机像素时钟信号发送到所述主芯片，以及用于配置从所述主芯片到所述主相机和所述副相机中的至少一个的路径的开关。

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