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1. 发明申请

US20080111224A1 Multi stack package and method of fabricating the same 审中-公开
标题翻译：多堆叠封装及其制造方法
公开(公告)号：US20080111224A1
公开(公告)日：2008-05-15
申请号：US11790962
申请日：2007-04-30
申请人： Hak-kyoon Byun , Tae-je Cho , Jong-bo Shim , Sang-uk Han
发明人： Hak-kyoon Byun , Tae-je Cho , Jong-bo Shim , Sang-uk Han
IPC分类号： H01L23/02 , H01L21/00
CPC分类号： H01L23/3128 , H01L23/12 , H01L24/32 , H01L24/48 , H01L24/73 , H01L25/0657 , H01L25/105 , H01L25/50 , H01L2224/32145 , H01L2224/32225 , H01L2224/32245 , H01L2224/48227 , H01L2224/48465 , H01L2224/73215 , H01L2224/73265 , H01L2225/0651 , H01L2225/1023 , H01L2225/1058 , H01L2225/1088 , H01L2225/1094 , H01L2924/00014 , H01L2924/01079 , H01L2924/10253 , H01L2924/14 , H01L2924/15151 , H01L2924/15311 , H01L2924/15331 , H01L2924/181 , H01L2924/18165 , H01L2924/3511 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： Embodiments of the present invention provide a MSP having an upper and lower package, with a recess opening in the substrate of the upper package. The upper package may also include multiple stacked semiconductor chips. A lower package may include a substrate and at least one semiconductor chip. During assembly, portions of a lower package are placed into the recess opening in the substrate of the upper package. The beneficial result is a two-package MSP assembly with a reduced total height. In addition, the size and pitch of solder balls or other joints between the upper package substrate and the lower package substrate may also be reduced.
摘要翻译：本发明的实施例提供了具有上和下封装的MSP，在上封装的基板中具有凹口。上封装还可以包括多个堆叠的半导体芯片。下封装可以包括基板和至少一个半导体芯片。在组装期间，下部包装的部分被放置在上部包装的基底中的凹部开口中。有利的结果是具有降低的总高度的双封装MSP组件。此外，也可以减小上封装基板和下封装基板之间的焊球或其他接头的尺寸和间距。

2. 发明申请

US20080160725A1 SEMICONDUCTOR DIE PICK UP APPARATUS AND METHOD THEREOF 审中-公开
标题翻译： SEMICONDUCTOR DIE PICK UP APPARATUS及其方法
公开(公告)号：US20080160725A1
公开(公告)日：2008-07-03
申请号：US11959299
申请日：2007-12-18
申请人： Hak-Kyoon BYUN , Hyun-Jung SONG , Jong-Bo SHIM
发明人： Hak-Kyoon BYUN , Hyun-Jung SONG , Jong-Bo SHIM
IPC分类号： H01L21/304 , H01L21/683
CPC分类号： H01L21/67132 , H01L21/6831 , H01L24/27 , H01L24/29 , H01L24/75 , H01L24/83 , H01L2224/75735 , H01L2224/83191 , H01L2924/14 , H01L2924/00
摘要： According to example embodiments, an apparatus for picking up a semiconductor die includes an electromagnetic collet unit configured to selectively generate an attractive force between the electromagnetic collet unit and a magnetic wafer adhesive tape disposed on a surface of the semiconductor die. The apparatus further includes a transfer head unit attached to the electromagnetic collet unit, the transfer head unit structured to move the semiconductor die picked up by the collet unit through a drive of a drive device.
摘要翻译：根据示例性实施例，用于拾取半导体管芯的设备包括电磁夹头单元，其被配置为选择性地在电磁夹头单元和设置在半导体管芯的表面上的磁性晶片粘合带之间产生吸引力。该装置还包括附接到电磁夹头单元的传送头单元，传送头单元构造成通过驱动装置的驱动来移动由夹头单元拾取的半导体管芯。

3. 发明授权

US07211889B2 Semiconductor package and method for manufacturing the same 有权
标题翻译：半导体封装及其制造方法
公开(公告)号：US07211889B2
公开(公告)日：2007-05-01
申请号：US10199343
申请日：2002-07-19
申请人： Jong Bo Shim
发明人： Jong Bo Shim
IPC分类号： H01L23/12
CPC分类号： H01L23/49833 , H01L23/10 , H01L23/16 , H01L23/36 , H01L2224/16 , H01L2924/01078 , H01L2924/12044 , H01L2924/15311 , H01L2924/16195
摘要： A semiconductor package includes a wiring board, a semiconductor chip flip-chip bonded to the wiring board, an adhesive coated on the wiring board, a stiffener ring attached to the wiring board, and a heat spreader attached to the stiffener ring and the semiconductor chip. The stiffener ring includes a window through which the semiconductor chip is exposed and multiple through holes. A thermal interface material (TIM) coated on the back surface of the semiconductor chip. The stiffener ring is attached to the heat spreader by portions of the adhesive squeezed onto the upper surface of the stiffener ring via the through holes, and the semiconductor chip is attached to the heat spreader by the TIM. A method for manufacturing a semiconductor package includes: flip-chip bonding a semiconductor chip to a wiring board; coating an adhesive on the wiring board; and attaching a stiffener ring to the wiring board. The stiffener ring includes a window through which the semiconductor chip is exposed and through holes. The stiffener ring is attached to a heat spreader by portions of the adhesive squeezed onto the upper surface of the stiffener ring via the through holes, and the semiconductor chip is attached to the heat spreader by the TIM.
摘要翻译：半导体封装包括布线板，与布线板接合的半导体芯片倒装芯片，涂覆在布线板上的粘合剂，附着在布线板上的加强环，以及附着在加强环和半导体芯片上的散热器。加强环包括露出半导体芯片的窗口和多个通孔。涂覆在半导体芯片背面的热界面材料（TIM）。加强环通过通过通孔挤压到加强环的上表面上的粘合剂的一部分附着到散热器上，并且半导体芯片通过TIM附接到散热器。一种半导体封装的制造方法，包括：将半导体芯片倒装芯片接合到布线板; 在接线板上涂上粘合剂; 以及将加强环附接到所述布线板。加强环包括露出半导体芯片的窗口和通孔。加强环通过通过通孔挤压到加强环的上表面上的粘合剂的一部分附着到散热器上，并且半导体芯片通过TIM附接到散热器。

4. 发明申请

US20070034401A1 Circuit board and manufacturing method thereof 审中-公开
标题翻译：电路板及其制造方法
公开(公告)号：US20070034401A1
公开(公告)日：2007-02-15
申请号：US11342845
申请日：2006-01-31
申请人： Jong-Bo Shim
发明人： Jong-Bo Shim
IPC分类号： H05K1/11 , H05K1/09
CPC分类号： H05K1/111 , H01L23/49816 , H01L23/49827 , H01L24/48 , H01L2224/48227 , H01L2224/73265 , H01L2924/00014 , H01L2924/181 , H05K3/06 , H05K3/4007 , H05K2201/0367 , H05K2201/0373 , H05K2203/0369 , Y02P70/611 , Y10T29/4913 , Y10T29/49147 , Y10T29/49151 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A circuit board may have a metal land supporting a pillar. The pillar may be fabricated by half-etching the metal land. An insulating layer may be provided on the circuit board so that the pillar of the metal land may be exposed through the insulating layer.
摘要翻译：电路板可以具有支撑柱的金属片。该柱可以通过半蚀刻金属焊盘来制造。可以在电路板上设置绝缘层，使得金属焊盘的柱可以通过绝缘层露出。

5. 发明授权

US06847109B2 Area array semiconductor package and 3-dimensional stack thereof 有权
标题翻译：面阵列半导体封装及其三维叠层
公开(公告)号：US06847109B2
公开(公告)日：2005-01-25
申请号：US10406447
申请日：2003-04-04
申请人： Jong Bo Shim
发明人： Jong Bo Shim
IPC分类号： H01L23/28 , H01L21/44 , H01L21/56 , H01L23/31 , H01L23/48 , H01L23/538 , H01L25/10
CPC分类号： H01L24/97 , H01L21/561 , H01L23/3128 , H01L23/5384 , H01L23/5387 , H01L23/5389 , H01L24/48 , H01L24/49 , H01L25/105 , H01L2224/05599 , H01L2224/32225 , H01L2224/45099 , H01L2224/48091 , H01L2224/48227 , H01L2224/48465 , H01L2224/49175 , H01L2224/73265 , H01L2224/85399 , H01L2224/97 , H01L2225/1023 , H01L2225/1058 , H01L2924/00014 , H01L2924/01006 , H01L2924/01033 , H01L2924/01079 , H01L2924/01082 , H01L2924/12042 , H01L2924/15311 , H01L2924/15331 , H01L2924/181 , H01L2224/85 , H01L2224/83 , H01L2924/00 , H01L2924/00012 , H01L2224/45015 , H01L2924/207
摘要： An area array type semiconductor package suitable for use in the formation of a 3-dimensional stack of the area array type packages. The area array type semiconductor package includes a circuit board, typically a tape circuit board, a semiconductor chip, bonding wires, an encapsulation body, solder posts, and solder balls. A plurality of the area array type semiconductor packages can be electrically connected through the corresponding solder balls and solder posts on adjacent packages to form semiconductor stack packages.
摘要翻译：一种面阵列型半导体封装，适用于形成区域阵列型封装的三维叠层。该区域阵列型半导体封装包括电路板，通常为带状电路板，半导体芯片，接合线，封装体，焊点和焊球。多个区域阵列型半导体封装可以通过相邻封装上的相应焊球和焊料柱电连接以形成半导体堆叠封装。

6. 发明申请

US20140374902A1 STACK TYPE SEMICONDUCTOR PACKAGE 有权
标题翻译：堆叠型半导体封装
公开(公告)号：US20140374902A1
公开(公告)日：2014-12-25
申请号：US14267259
申请日：2014-05-01
申请人： Jang-Woo LEE , Jong-Bo SHIM , Kyoung-sei CHOI
发明人： Jang-Woo LEE , Jong-Bo SHIM , Kyoung-sei CHOI
IPC分类号： H01L23/00 , H01L23/36
CPC分类号： H01L23/36 , H01L23/367 , H01L23/3736 , H01L23/5389 , H01L24/03 , H01L24/05 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/73 , H01L24/81 , H01L25/105 , H01L25/50 , H01L2224/03312 , H01L2224/0346 , H01L2224/0401 , H01L2224/04042 , H01L2224/04105 , H01L2224/05552 , H01L2224/05553 , H01L2224/05554 , H01L2224/05555 , H01L2224/05573 , H01L2224/05578 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/131 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13169 , H01L2224/16225 , H01L2224/1703 , H01L2224/17181 , H01L2224/17519 , H01L2224/32225 , H01L2224/45124 , H01L2224/45139 , H01L2224/45144 , H01L2224/45147 , H01L2224/45155 , H01L2224/45169 , H01L2224/48091 , H01L2224/48227 , H01L2224/73204 , H01L2224/73253 , H01L2224/73265 , H01L2224/81191 , H01L2224/81192 , H01L2224/94 , H01L2225/1023 , H01L2225/1058 , H01L2225/1094 , H01L2924/00014 , H01L2924/12042 , H01L2924/15311 , H01L2924/15331 , H01L2924/181 , H01L2924/18161 , H01L2924/00012 , H01L2224/11 , H01L2924/014 , H01L2224/03 , H01L2924/00 , H01L2224/45015 , H01L2924/207
摘要： A stack type semiconductor package includes: a lower semiconductor package including a lower package substrate, and a lower semiconductor chip which is mounted on the lower package substrate and includes a first surface facing a top surface of the lower package substrate and a second surface opposite to the first surface; an upper semiconductor package including an upper package substrate and an upper semiconductor chip which is mounted on the upper package substrate; an inter-package connection unit which connects the lower package substrate and the upper package substrate; a heat dissipation member which is formed on the second surface of the lower semiconductor chip; and an interconnection unit which is formed on a bottom surface of the upper package substrate, and is adhered to the heat dissipation member to connect the lower semiconductor chip and the upper package substrate.
摘要翻译：堆叠型半导体封装包括：下半导体封装，包括下封装衬底，以及下半导体芯片，其安装在下封装衬底上，并且包括面向下封装衬底的顶表面的第一表面和与下封装衬底相对的第二表面第一面; 上半导体封装，包括上封装基板和安装在上封装基板上的上半导体芯片; 连接下封装基板和上封装基板的封装间连接单元; 形成在下半导体芯片的第二表面上的散热构件; 以及互连单元，其形成在所述上封装基板的底表面上，并且粘附到所述散热构件以连接所述下半导体芯片和所述上封装基板。

7. 发明授权

US07304371B2 Lead frame having a lead with a non-uniform width 有权
标题翻译：引线框架具有不均匀宽度的引线
公开(公告)号：US07304371B2
公开(公告)日：2007-12-04
申请号：US11106514
申请日：2005-04-15
申请人： Tae-Hun Kim , Jong-Bo Shim , Tae-Je Cho
发明人： Tae-Hun Kim , Jong-Bo Shim , Tae-Je Cho
IPC分类号： H01L23/495
CPC分类号： H01L23/49558 , H01L23/49541 , H01L2924/0002 , H01L2924/00
摘要： A lead frame may include a plurality of leads, each having a bonding portion electrically connected to a semiconductor chip and an attaching portion. A tape may be provided on the attaching portions of the leads. The attaching portion of each lead may have a width that is smaller than the width of another portion of the lead. A plating layer may be provided on the attaching portion. The lead frame may be implemented in a semiconductor package.
摘要翻译：引线框架可以包括多个引线，每个引线具有电连接到半导体芯片和附接部分的接合部分。可以在引线的附接部分上设置带。每个引线的安装部分可以具有比引线的另一部分的宽度小的宽度。可以在安装部上设置镀层。引线框可以在半导体封装中实现。

8. 发明申请

US20180040548A1 SEMICONDUCTOR PACKAGE INCLUDING A REWIRING LAYER WITH AN EMBEDDED CHIP 有权
公开(公告)号：US20180040548A1
公开(公告)日：2018-02-08
申请号：US15468294
申请日：2017-03-24
申请人： JI-HWANG KIM , JONG-BO SHIM , CHA-JEA JO , WON-IL LEE
发明人： JI-HWANG KIM , JONG-BO SHIM , CHA-JEA JO , WON-IL LEE
IPC分类号： H01L23/498 , H01L25/00 , H01L23/00 , H01L25/065 , H01L23/31
CPC分类号： H01L23/49838 , H01L23/3128 , H01L23/49827 , H01L24/09 , H01L25/0652 , H01L25/0657 , H01L25/50 , H01L2224/0401 , H01L2225/06513 , H01L2225/06517 , H01L2225/06562 , H01L2225/06586
摘要： A semiconductor package includes a substrate, a rewiring layer, a plurality of semiconductor chip stack structures, and a second semiconductor chip. The rewiring layer is disposed on an upper surface of the substrate. The rewiring layer includes a concave portion. The semiconductor chip stack structures include a plurality of first semiconductor chips. The first semiconductor chips are disposed on the rewiring layer. The first semiconductor chips are spaced apart from each other in a horizontal direction. The second semiconductor chip is disposed within the concave portion. The second semiconductor chip is configured to electrically connect each of the plurality of semiconductor chip stack structures to each other.

9. 发明申请

US20090265928A1 Circuit board and manufacturing method thereof 审中-公开
标题翻译：电路板及其制造方法
公开(公告)号：US20090265928A1
公开(公告)日：2009-10-29
申请号：US12458088
申请日：2009-06-30
申请人： Jong-Bo SHIM
发明人： Jong-Bo SHIM
IPC分类号： H05K3/30
CPC分类号： H05K1/111 , H01L23/49816 , H01L23/49827 , H01L24/48 , H01L2224/48227 , H01L2224/73265 , H01L2924/00014 , H01L2924/181 , H05K3/06 , H05K3/4007 , H05K2201/0367 , H05K2201/0373 , H05K2203/0369 , Y02P70/611 , Y10T29/4913 , Y10T29/49147 , Y10T29/49151 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A circuit board may have a metal land supporting a pillar. The pillar may be fabricated by half-etching the metal land. An insulating layer may be provided on the circuit board so that the pillar of the metal land may be exposed through the insulating layer.
摘要翻译：电路板可以具有支撑柱的金属片。该柱可以通过半蚀刻金属焊盘来制造。可以在电路板上设置绝缘层，使得金属焊盘的柱可以通过绝缘层露出。

10. 发明申请

US20130161836A1 SEMICONDUCTOR PACKAGE HAVING INTERPOSER COMPRISING A PLURALITY OF SEGMENTS 审中-公开
标题翻译：具有包含多个部分的插件的半导体封装
公开(公告)号：US20130161836A1
公开(公告)日：2013-06-27
申请号：US13584637
申请日：2012-08-13
申请人： Kun-Dae YEOM , Young-Min KIM , Jong-Bo SHIM , Woo-Dong LEE
发明人： Kun-Dae YEOM , Young-Min KIM , Jong-Bo SHIM , Woo-Dong LEE
IPC分类号： H01L23/48
CPC分类号： H01L25/105 , H01L21/563 , H01L23/13 , H01L23/3128 , H01L23/49811 , H01L23/49822 , H01L23/49827 , H01L23/49833 , H01L24/16 , H01L24/48 , H01L24/73 , H01L2224/131 , H01L2224/16145 , H01L2224/16146 , H01L2224/16225 , H01L2224/16227 , H01L2224/32145 , H01L2224/32225 , H01L2224/48227 , H01L2224/73265 , H01L2225/0651 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06565 , H01L2225/06568 , H01L2225/1023 , H01L2225/1041 , H01L2225/1058 , H01L2225/107 , H01L2924/00014 , H01L2924/15311 , H01L2924/15321 , H01L2924/181 , H01L2924/18161 , H01L2924/3511 , H01L2924/00012 , H01L2924/00 , H01L2924/014 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： Provided is a semiconductor package comprising a substrate, a semiconductor chip formed on the substrate, and an interposer including a plurality of segments which are separated from each other and arranged on the substrate to surround the semiconductor chip. And a stacked package for multiple chips including the semiconductor package with a plurality of segments of an interposer is provided.
摘要翻译：提供了一种半导体封装，其包括基板，形成在基板上的半导体芯片，以及包括彼此分离并布置在基板上以围绕半导体芯片的多个段的中介层。并且提供了一种用于多个芯片的堆叠封装，其包括具有插入件的多个段的半导体封装。

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