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    • 2. 发明授权
    • State saving and restoration in reprogrammable FPGAs
    • 可再编程FPGA中的状态保存和恢复
    • US5844422A
    • 1998-12-01
    • US748443
    • 1996-11-13
    • Stephen M. TrimbergerJonathan S. Rose
    • Stephen M. TrimbergerJonathan S. Rose
    • H03K19/177H03K19/173
    • H03K19/17772H03K19/1776
    • Structures for saving states of memory cells in an FPGA while the FPGA is being configured are shown. Structures for saving flip flop states, lookup table configurations, and block RAM states are specifically described. Structures are described having (1) a SAVE STATE bit for saving the state of each flip flop, each lookup table RAM, and each block RAM. With these structures, each storage unit can be selectively restored. (2) a SAVE STATE bit for each row(column) of logic blocks in the FPGA. In such structures it is possible with a single SAVE STATE signal to selectively save or restore every memory element in the row, possibly including flip flops, lookup tables, and blocks of RAM. Several structures and methods for providing the SAVE STATE signal are also described. These include: (1) bits in the bitstream of a first configuration which indicate which memory units of the first configuration are to be retained during a second configuration; (2) bits at the beginning of the bitstream of a second configuration which indicate which memory units of the first configuration are to be retained during a second configuration; and (3) circuit loadable during operation of a first configuration which indicates which memory units of the first configuration are to be retained during a second configuration.
    • 显示了在配置FPGA时保存FPGA中存储单元状态的结构。 具体描述了用于保存触发器状态,查找表配置和阻塞RAM状态的结构。 描述了具有(1)用于保存每个触发器,每个查找表RAM和每个块RAM的状态的保存状态位的结构。 利用这些结构,可以选择性地恢复每个存储单元。 (2)FPGA中逻辑块的每行(列)的SAVE STATE位。 在这种结构中,单个SAVE STATE信号可以选择性地保存或恢复该行中的每个存储元件,可能包括触发器,查找表和RAM块。 还描述了用于提供SAVE STATE信号的几种结构和方法。 这些包括:(1)第一配置的比特流中的比特,其指示在第二配置期间将保留第一配置的哪些存储单元; (2)位在第二配置的比特流的开头,指示在第二配置期间将保留第一配置的哪些存储单元; 以及(3)在第一配置的操作期间可加载的电路,其指示在第二配置期间将保留所述第一配置的哪些存储器单元。