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1. 发明授权

US07474189B1 Circuit board embedded inductor 有权
标题翻译：电路板嵌入式电感
公开(公告)号：US07474189B1
公开(公告)日：2009-01-06
申请号：US11301039
申请日：2005-12-12
申请人： David Dening , Steve Dorn , Milind Shah , Yang Rao , Michael Kay , Jon Jorgenson
发明人： David Dening , Steve Dorn , Milind Shah , Yang Rao , Michael Kay , Jon Jorgenson
IPC分类号： H01F5/00
CPC分类号： H01F17/0013 , H01F2017/002 , H01F2017/048 , H05K1/165 , H05K3/4626 , H05K3/4652 , H05K3/4655 , H05K2201/0187 , H05K2201/0209 , H05K2201/086 , Y10T29/4902
摘要： A circuit board having an embedded inductor and a process for making the circuit board is provided. In general, the process begins by providing a core structure including a dielectric core layer and a first metal layer on a top surface of the dielectric core layer. The first metal layer is etched to form first inductor windings. A material, such as an epoxy material, including magnetic filler material is deposited over the first inductor windings. Thereafter, a prepreg layer is placed over and attached to the material deposited over the first inductor windings to form the circuit board having the embedded inductor.
摘要翻译：提供具有嵌入式电感器的电路板和制造电路板的工艺。通常，该方法开始于在介质芯层的顶表面上提供包括介电芯层和第一金属层的芯结构。第一金属层被蚀刻以形成第一电感器绕组。包括磁性填充材料在内的诸如环氧材料的材料沉积在第一电感器绕组上。此后，将预浸料层放置在沉积在第一电感器绕组上的材料上并附着到形成具有嵌入式电感器的电路板。

2. 发明申请

US20050176209A1 Embedded passive components 审中-公开
标题翻译：嵌入式无源元件
公开(公告)号：US20050176209A1
公开(公告)日：2005-08-11
申请号：US10366924
申请日：2003-02-14
申请人： Jon Jorgenson , Milind Shah , Victor Steel
发明人： Jon Jorgenson , Milind Shah , Victor Steel
IPC分类号： H05K1/16 , H05K3/46 , H01L21/20 , G06F17/50 , H01L29/00
CPC分类号： H05K1/162 , H05K1/165 , H05K1/167 , H05K3/4652 , H05K2201/0347 , H05K2201/0355 , H05K2201/0959 , H05K2201/09763
摘要： The present invention embeds passive components within a multilayer substrate used for mounting integrated circuits and other electronic components to form an electronic module or circuit board. During construction of the multilayer substrate, passive components are attached to an inside surface of a metallic foil layer. The inside surface of the metallic foil layer is then laminated to another metallic foil layer, such that the foil layers are parallel to but separated from each other. As such, the passive component is embedded within the multilayer substrate. Contacts are formed for the passive component by etching away portions of the foil layer on which the passive component resides. Electrical connections can be routed in the foil to effectively couple the passive component to a circuit formed on the multilayer substrate as desired. The embedded passive components can take various forms, such as capacitors, inductors, and resistors.
摘要翻译：本发明将无源部件嵌入用于安装集成电路和其他电子部件的多层基板中，以形成电子模块或电路板。在多层基板的构造期间，将无源部件附着到金属箔层的内表面。然后将金属箔层的内表面层压到另一金属箔层上，使得箔层彼此平行但分开。因此，被动部件嵌入在多层基板内。通过蚀刻去除被动部件所在的箔层的部分，为无源部件形成触点。电连接可以在箔中布线以有效地将无源部件耦合到根据需要在多层基板上形成的电路。嵌入式无源器件可以采取各种形式，如电容器，电感器和电阻器。

3. 发明授权

US06996892B1 Circuit board embedded inductor 有权
公开(公告)号：US06996892B1
公开(公告)日：2006-02-14
申请号：US11089297
申请日：2005-03-24
申请人： David Dening , Steve Dorn , Milind Shah , Yang Rao , Michael Kay , Jon Jorgenson
发明人： David Dening , Steve Dorn , Milind Shah , Yang Rao , Michael Kay , Jon Jorgenson
IPC分类号： H01F7/06
CPC分类号： H01F17/0013 , H01F2017/002 , H01F2017/048 , H05K1/165 , H05K3/4626 , H05K3/4652 , H05K3/4655 , H05K2201/0187 , H05K2201/0209 , H05K2201/086 , Y10T29/4902
摘要： A circuit board having an embedded inductor and a process for making the circuit board is provided. In general, the process begins by providing a core structure including a dielectric core layer and a first metal layer on a top surface of the dielectric core layer. The first metal layer is etched to form first inductor windings. A material, such as an epoxy material, including magnetic filler material is deposited over the first inductor windings. Thereafter, a prepreg layer is placed over and attached to the material deposited over the first inductor windings to form the circuit board having the embedded inductor.

4. 发明授权

US06884661B1 Method of fabricating posts over integrated heat sink metallization to enable flip chip packaging of GaAs devices 有权
标题翻译：通过集成散热器金属化制造焊点以实现GaAs器件的倒装芯片封装的方法
公开(公告)号：US06884661B1
公开(公告)日：2005-04-26
申请号：US10701754
申请日：2003-11-04
申请人： Thomas Scott Morris , Milind Shah , Jon Jorgenson
发明人： Thomas Scott Morris , Milind Shah , Jon Jorgenson
IPC分类号： H01L21/60 , H01L23/367 , H01L23/485 , H01L21/48
CPC分类号： H01L24/13 , H01L23/367 , H01L23/3677 , H01L24/11 , H01L2224/05001 , H01L2224/05027 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/05166 , H01L2224/05171 , H01L2224/05184 , H01L2224/05572 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05666 , H01L2224/05671 , H01L2224/05684 , H01L2224/13099 , H01L2224/13144 , H01L2224/13147 , H01L2924/0001 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01079 , H01L2924/014 , H01L2924/10329 , H01L2924/3011 , H01L2924/00014
摘要： The present invention provides for attaching a Gallium Arsenide (GaAs) semiconductor die to a package using bumps formed over a metallic heat sink covering the output transistor area of the semiconductor die. In general, one or more bumps are formed on the metallic heat sink, thereby eliminating stress on the bumps caused by stress risers on the surface of the semiconductor die. In addition, the upper and lower surfaces of the bumps are substantially planar, thereby maximizing contact with the semiconductor die and the package and allowing maximum heat transfer. The planarization is due to the conforming contact surface of the solder. The combination of the bumps and the metallic heat sink provide an efficient way to reduce the thermal and electrical impedance of the die. In one embodiment, the bumps are substantially copper. In another embodiment, the bumps are substantially gold.
摘要翻译：本发明提供了使用覆盖半导体管芯的输出晶体管区域的金属散热器上形成的凸块来将砷化镓（GaAs）半导体管芯附着到封装上。通常，在金属散热器上形成一个或多个凸块，从而消除由半导体管芯的表面上的应力梯度引起的凸点上的应力。此外，凸块的上表面和下表面基本上是平面的，从而使与半导体管芯和封装件的接触最大化并允许最大的热传递。平坦化是由于焊料的一致的接触表面。凸块和金属散热器的组合提供了降低模具的热和电阻抗的有效方式。在一个实施例中，凸块基本上是铜。在另一个实施例中，凸块基本上是金。

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