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    • 1. 发明授权
    • Systems and methods for communication system control utilizing corrected forward error correction error location identifiers
    • 利用校正的前向纠错误差位置标识符进行通信系统控制的系统和方法
    • US07962049B2
    • 2011-06-14
    • US11954980
    • 2007-12-12
    • John P. MateoskyMichael Y. FrankelJean-Luc Archambault
    • John P. MateoskyMichael Y. FrankelJean-Luc Archambault
    • H04B10/06
    • H04L1/005H04L1/0057H04L1/0059H04L1/0066
    • The present invention provides systems and methods for communication system control utilizing corrected forward error correction (FEC) error location identifiers in multi-level modulation scheme systems. The present invention utilizes precise error correction information, available for each FEC block of a particular code (including, but not limited to, block codes and concatenated block codes employing iterative decoding as well as convolutional codes (including turbo codes) and low-density parity-check code (LDPC) class codes) used (e.g., Bose, Ray-Chaudhuri, Hocquenghem (BCH), Reed-Solomon, etc.), as a result of the FEC decoding process to provide feedback to close the loop for control of a demodulator (i.e., receiver). Each error location can be uniquely traced back to a particular sub-rate signal path, with running, post-FEC corrected BER (bit error rate) calculations generated on each sub-rate signal. Advantageously, this provides the ability to adjust thresholds and various other parameters to achieve and maintain error-free operation quickly.
    • 本发明提供了在多级调制方案系统中利用校正的前向纠错(FEC)错误位置标识符的通信系统控制的系统和方法。 本发明利用针对特定码的每个FEC块(包括但不限于采用迭代解码以及卷积码(包括turbo码)的块码和级联块码)和低密度奇偶校验码的精确纠错信息 - 使用的检验码(LDPC)类码)(例如,Bose,Ray-Chaudhuri,Hocquenghem(BCH),Reed-Solomon等),作为FEC解码处理的结果,提供反馈以关闭用于控制 解调器(即接收器)。 每个错误位置可以唯一地追溯到特定的子速率信号路径,其中每个子速率信号上产生运行的FEC后校正BER(误码率)计算。 有利地,这提供了调整阈值和各种其他参数以便快速实现和维持无差错操作的能力。
    • 2. 发明申请
    • SERIALIZER-DESERIALIZER CIRCUIT WITH MULTI-FORMAT AND MULTI-DATA RATE CAPABILITY
    • 具有多格式和多数据速率能力的串行编解码器电路
    • US20090147896A1
    • 2009-06-11
    • US11953305
    • 2007-12-10
    • Michael Y. FRANKELJohn P. MATEOSKYStephen B. ALEXANDRER
    • Michael Y. FRANKELJohn P. MATEOSKYStephen B. ALEXANDRER
    • H04L7/00
    • H04L27/2071H03M9/00
    • The present invention provides a serializer/deserializer (SERDES) circuit that can cover both client- and network-side interfaces for high-speed data rates. The present invention leverages commonality between the client and network (also known as line) side, and accommodates differences in a flexible manner. In one exemplary embodiment, the present invention provides a four-channel implementation to meet the requirement of both interfaces. The SERDES circuit can be capable of supporting both 40 Gb/s and 56 Gb/s data rates, can include an integrated DQPSK pre-coder and I/Q input/output signals, and can support RZ clock recovery. Additionally, the SERDES circuit can include differential coding support, electronic pre-emphasis, receiver-side electronic dispersion compensation, and the like.
    • 本发明提供了一种串行器/解串器(SERDES)电路,其可以覆盖用于高速数据速率的客户端和网络侧接口。 本发明利用客户端和网络(也称为线路)侧之间的通用性,并以灵活的方式适应差异。 在一个示例性实施例中,本发明提供了四通道实现以满足两个接口的要求。 SERDES电路能够支持40 Gb / s和56 Gb / s数据速率,可以包含集成的DQPSK预编码器和I / Q输入/输出信号,并且可以支持RZ时钟恢复。 此外,SERDES电路可以包括差分编码支持,电子预加重,接收机侧电子色散补偿等。
    • 5. 发明授权
    • Serializer-deserializer circuit with multi-format and multi-data rate capability
    • 具有多格式和多数据速率功能的串行器 - 解串器电路
    • US08582705B2
    • 2013-11-12
    • US11953305
    • 2007-12-10
    • Michael Y. FrankelJohn P. MateoskyStephen B. Alexander
    • Michael Y. FrankelJohn P. MateoskyStephen B. Alexander
    • H04L7/00
    • H04L27/2071H03M9/00
    • The present invention provides a serializer/deserializer (SERDES) circuit that can cover both client- and network-side interfaces for high-speed data rates. The present invention leverages commonality between the client and network (also known as line) side, and accommodates differences in a flexible manner. In one exemplary embodiment, the present invention provides a four-channel implementation to meet the requirement of both interfaces. The SERDES circuit can be capable of supporting both 40 Gb/s and 56 Gb/s data rates, can include an integrated DQPSK pre-coder and I/Q input/output signals, and can support RZ clock recovery. Additionally, the SERDES circuit can include differential coding support, electronic pre-emphasis, receiver-side electronic dispersion compensation, and the like.
    • 本发明提供了一种串行器/解串器(SERDES)电路,其可以覆盖用于高速数据速率的客户端和网络侧接口。 本发明利用客户端和网络(也称为线路)侧之间的通用性,并以灵活的方式适应差异。 在一个示例性实施例中,本发明提供了四通道实现以满足两个接口的要求。 SERDES电路能够支持40 Gb / s和56 Gb / s数据速率,可以包含集成的DQPSK预编码器和I / Q输入/输出信号,并且可以支持RZ时钟恢复。 此外,SERDES电路可以包括差分编码支持,电子预加重,接收机侧电子色散补偿等。
    • 8. 发明授权
    • Frame-interleaving systems and methods for 100G optical transport enabling multi-level optical transmission
    • 用于100G光传输的帧交错系统和方法,实现多级光传输
    • US08213446B2
    • 2012-07-03
    • US11964468
    • 2007-12-26
    • Kevin S. MeagherJohn P. Mateosky
    • Kevin S. MeagherJohn P. Mateosky
    • H04L12/28
    • H04J3/047H04J3/1652H04J3/1658H04L1/0071
    • The present invention provides frame-interleaving systems and methods for Optical Transport Unit K (OTUK) (i.e. Optical Transport Unit 4 (OTU4)), 100 Gb/s Ethernet (100 GbE), and other 100 Gb/s (100 G) optical transport enabling multi-level optical transmission. The frame-interleaving systems and methods of the present invention support the multiplexing of sub-rate clients, such as 10×10 Gb/s (10 G) clients, 2×40 Gb/s (40 G) plus 2×10 G clients, etc., into two 50 Gb/s (50 G) transport signals, four 25 Gb/s (25 G) transport signals, etc. that are forward error correction (FEC) encoded and carried on a single wavelength to provide useful, efficient, and cost-effective 100 G optical transport solutions today. In one exemplary configuration, a 100 G client signal or 100 G aggregate client signal carried over two or more channels is frame-deinterleaved, followed by even/odd sub-channel FEC encoding and framing. In another exemplary configuration, a 100 G client signal or 100 G aggregate client signal carried over two or more channels is received and processed by a single 100 G FEC framer, followed by frame-deinterleaving into two or more sub-rate channels.
    • 本发明提供了用于光传输单元K(OTUK)(即,光传输单元4(OTU4)),100Gb / s以太网(100GbE)和其他100Gb / s(100G)光学器件的帧交错系统和方法 运输启用多级光传输。 本发明的帧交错系统和方法支持诸如10×10Gb / s(10G)客户端,2×40Gb / s(40G)加2×10G客户端的子速率客户端的复用 等等,分为两个50Gb / s(50G)传输信号,四个25Gb / s(25G)传输信号等,其是在单个波长上编码和携带的前向纠错(FEC),以提供有用的, 高效,高性价比的100G光传输解决方案。 在一个示例性配置中,在两个或更多个信道上承载的100G客户端信号或100G聚合客户端信号被帧去交织,随后是偶数/奇数子信道FEC编码和成帧。 在另一示例性配置中,由两个或更多个信道承载的100G客户端信号或100G聚合客户端信号由单个100G FEC成帧器接收和处理,随后进行帧去交错至两个或多个子速率信道。
    • 9. 发明申请
    • FRAME-INTERLEAVING SYSTEMS AND METHODS FOR 100G OPTICAL TRANSPORT ENABLING MULTI-LEVEL OPTICAL TRANSMISSION
    • 用于100G光传输的框架交互系统和方法启用多级光传输
    • US20090169204A1
    • 2009-07-02
    • US11964468
    • 2007-12-26
    • Kevin S. MeagherJohn P. Mateosky
    • Kevin S. MeagherJohn P. Mateosky
    • H04J14/00
    • H04J3/047H04J3/1652H04J3/1658H04L1/0071
    • The present invention provides frame-interleaving systems and methods for Optical Transport Unit K (OTUK) (i.e. Optical Transport Unit 4 (OTU4)), 100 Gb/s Ethernet (100 GbE), and other 100 Gb/s (100 G) optical transport enabling multi-level optical transmission. The frame-interleaving systems and methods of the present invention support the multiplexing of sub-rate clients, such as 10×10 Gb/s (10 G) clients, 2×40 Gb/s (40 G) plus 2×10 G clients, etc., into two 50 Gb/s (50 G) transport signals, four 25 Gb/s (25 G) transport signals, etc. that are forward error correction (FEC) encoded and carried on a single wavelength to provide useful, efficient, and cost-effective 100 G optical transport solutions today. In one exemplary configuration, a 100 G client signal or 100 G aggregate client signal carried over two or more channels is frame-deinterleaved, followed by even/odd sub-channel FEC encoding and framing. In another exemplary configuration, a 100 G client signal or 100 G aggregate client signal carried over two or more channels is received and processed by a single 100 G FEC framer, followed by frame-deinterleaving into two or more sub-rate channels.
    • 本发明提供了用于光传输单元K(OTUK)(即,光传输单元4(OTU4)),100Gb / s以太网(100GbE)和其他100Gb / s(100G)光学器件的帧交错系统和方法 运输启用多级光传输。 本发明的帧交织系统和方法支持诸如10×10Gb / s(10G)客户端,2×40Gb / s(40G)×2×10G客户端等的子速率客户端的复用为2 50Gb / s(50G)传输信号,四个25Gb / s(25G)传输信号等,其是在单个波长上编码和携带的前向纠错(FEC),以提供有用,高效和成本有效的 100 G光传输解决方案。 在一个示例性配置中,在两个或更多个信道上承载的100G客户端信号或100G聚合客户端信号被帧去交织,随后是偶数/奇数子信道FEC编码和成帧。 在另一示例性配置中,由两个或更多个信道承载的100G客户端信号或100G聚合客户端信号由单个100G FEC成帧器接收和处理,随后进行帧去交错至两个或多个子速率信道。
    • 10. 发明申请
    • HIGH-SPEED OPTICAL TRANSCEIVER FOR INFINIBAND AND ETHERNET
    • 用于INFINIBAND和以太网的高速光纤收发器
    • US20090022497A1
    • 2009-01-22
    • US12166537
    • 2008-07-02
    • John P. MateoskyMichael Y. Frankel
    • John P. MateoskyMichael Y. Frankel
    • H04B10/00
    • H04B10/40H04B10/27H04J14/0227H04L1/004H04L1/0056H04L27/2096H04L27/223
    • The present invention provides a high-speed 100G optical transceiver for InfiniBand and Ethernet with associated mapping to frame InfiniBand and Ethernet into GFP-T. The optical transceiver utilizes an architecture which relies on standards-compliant (i.e., multi-sourced) physical client interfaces. These client interfaces are back-ended with flexible, programmable Field Programmable Gate Array (FPGA) modules to accomplish either InfiniBand or Ethernet protocol control, processing, re-framing, and the like. Next, signals are encoded with Forward Error Correction (FEC) and can include additional Optical Transport Unit (OTU) compliant framing structures. The resulting data is processed appropriately for the subsequent optical re-transmission, such as, for example, with differential encoding, Gray encoding, I/Q Quadrature encoding, and the like. The data is sent to an optical transmitter block and modulated onto an optical carrier. Also, the same process proceeds in reverse on the receive side.
    • 本发明提供了用于InfiniBand和以太网的高速100G光收发器,具有将InfiniBand和以太网格式化成GFP-T的相关映射。 光收发器利用依赖于符合标准(即多源)物理客户端接口的架构。 这些客户端接口具有灵活的,可编程的现场可编程门阵列(FPGA)模块,可实现InfiniBand或以太网协议控制,处理,重新构建等功能。 接下来,信号用前向纠错(FEC)进行编码,并且可以包括额外的光传输单元(OTU)兼容框架结构。 对于随后的光学重传,例如用差分编码,格雷编码,I / Q正交编码等适当地处理所得到的数据。 将数据发送到光发射机模块并调制到光载波上。 而且,相同的处理在接收侧进行相反的处理。