专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08433028B2 Latency locked loop circuit for driving a buffer circuit 有权
标题翻译：用于驱动缓冲电路的延迟锁定环路
公开(公告)号：US08433028B2
公开(公告)日：2013-04-30
申请号：US12795608
申请日：2010-06-07
申请人： John M. Khoury , Eduardo Viegas , Richard Beale
发明人： John M. Khoury , Eduardo Viegas , Richard Beale
IPC分类号： H03D3/24
CPC分类号： H03L7/0818
摘要： In an embodiment, a circuit includes a buffer circuit including a buffer input and an output terminal and a latency locked loop (LLL) circuit. The LLL circuit includes a signal input for receiving an input signal, a feedback input coupled to the output terminal, and a signal output coupled to the buffer input. The LLL circuit is configured to control a propagation delay between the signal input and the signal output to produce a substantially constant total delay from the signal input to the output terminal.
摘要翻译：在一个实施例中，电路包括缓冲器电路，其包括缓冲器输入端和输出端子以及等待时间锁定环路（LLL）电路。 LLL电路包括用于接收输入信号的信号输入，耦合到输出端的反馈输入和耦合到缓冲器输入的信号输出。 LLL电路被配置为控制信号输入和信号输出之间的传播延迟，以从信号输入到输出端产生基本恒定的总延迟。

2. 发明申请

US20120229211A1 AMPLIFIER USING FAST DISCHARGING REFERENCE 有权
标题翻译：放大器使用快速放大参考
公开(公告)号：US20120229211A1
公开(公告)日：2012-09-13
申请号：US13045233
申请日：2011-03-10
申请人： Pavel Konecny , Jinwen Xiao , John M. Khoury
发明人： Pavel Konecny , Jinwen Xiao , John M. Khoury
IPC分类号： H03F3/217 , H03K3/00
CPC分类号： H03K7/08 , H03F3/2173 , H03K17/166 , H03K2217/0027 , H03K2217/0045
摘要： Techniques are disclosed relating to charging and discharging a gate of transistor. In one embodiment, an apparatus is disclosed that includes a driver configured to discharge a gate of a transistor. The driver is configured to discharge the gate at a first rate until reaching a Miller plateau for the transistor, and to discharge the gate at a second rate after reaching the Miller plateau. In such an embodiment, the first rate is greater than the second rate. In some embodiments, the driver is also configured to charge the gate of the transistor at a third rate until reaching a Miller plateau for the transistor, and to charge the gate at a fourth rate after reaching the Miller plateau, the third rate being greater than the fourth rate. In some embodiments, the apparatus is a class D amplifier.
摘要翻译：公开了关于对晶体管的栅极进行充电和放电的技术。在一个实施例中，公开了一种装置，其包括被配置为对晶体管的栅极进行放电的驱动器。驱动器被配置为以第一速率排放门，直到达到晶体管的Miller平台，并且在达到Miller平台之后以第二速率排出门。在这种实施例中，第一速率大于第二速率。在一些实施例中，驱动器还被配置为以三速对晶体管的栅极充电，直到达到晶体管的Miller平台为止，并且在达到Miller平台之后以第四速率对栅极充电，第三速率大于第四率。在一些实施例中，该装置是D类放大器。

3. 发明申请

US20100171540A1 System and Method of Changing a PWM Power Spectrum 有权
标题翻译：改变PWM功率谱的系统和方法
公开(公告)号：US20100171540A1
公开(公告)日：2010-07-08
申请号：US12729000
申请日：2010-03-22
申请人： Richard Gale Beale , John M. Khoury
发明人： Richard Gale Beale , John M. Khoury
IPC分类号： H03K3/01
CPC分类号： H03K7/08 , H03F1/26 , H03F3/2173 , H03K11/00
摘要： In a particular embodiment, a circuit device includes a pulse edge control circuit to receive at least one pulse-width modulated (PWM) signal from a PWM source. The pulse edge control circuit is adapted to selectively invert and swap the at least one PWM signal with a logic-inverted duty-cycle complement of the at least one PWM signal at discrete time intervals to produce at least one modulated PWM signal having a changed power spectrum. The pulse edge control circuit provides the at least one modulated PWM signal to at least one output of the pulse edge control circuit.
摘要翻译：在特定实施例中，电路装置包括脉冲边缘控制电路，以从PWM源接收至少一个脉冲宽度调制（PWM）信号。脉冲沿控制电路适于以离散时间间隔以至少一个PWM信号的逻辑反相占空比补码选择性地反转和交换至少一个PWM信号，以产生具有改变的功率的至少一个调制的PWM信号光谱。脉冲沿控制电路将至少一个调制的PWM信号提供给脉冲沿控制电路的至少一个输出端。

4. 发明申请

US20090243745A1 SYSTEM AND METHOD OF SHAPING A POWER SPECTRUM IN PWM AMPLIFIERS 失效
标题翻译：在PWM放大器中形成功率谱的系统和方法
公开(公告)号：US20090243745A1
公开(公告)日：2009-10-01
申请号：US12208535
申请日：2008-09-11
申请人： Jeffrey D. Alderson , John M. Khoury , Richard Gale Beale
发明人： Jeffrey D. Alderson , John M. Khoury , Richard Gale Beale
IPC分类号： H03K7/08
CPC分类号： H03K7/08
摘要： In a particular embodiment, a circuit device is disclosed that includes a data generator adapted to output a random pulse sequence having a particular spectral shape. The circuit device further includes a pulse edge control circuit to selectively apply a carrier suppression operation to at least one pulse-width modulated (PWM) signal in response to the random pulse sequence to produce at least one modulated PWM output signal. The spectral energy associated with a PWM carrier of the modulated PWM output signal at a carrier frequency and associated harmonics is changed such that the modulated PWM output signal has a spectral shape defined by the particular spectral shape.
摘要翻译：在特定实施例中，公开了一种电路装置，其包括适于输出具有特定光谱形状的随机脉冲序列的数据发生器。电路装置还包括脉冲边缘控制电路，用于响应于随机脉冲序列选择性地对至少一个脉冲宽度调制（PWM）信号施加载波抑制操作，以产生至少一个调制的PWM输出信号。与载波频率和相关谐波的调制PWM输出信号的PWM载波相关联的频谱能量被改变，使得调制的PWM输出信号具有由特定光谱形状限定的光谱形状。

5. 发明授权

US06869091B1 Method for enhancing the physical characteristics of a suspension component 有权
标题翻译：用于增强悬浮组分的物理特性的方法
公开(公告)号：US06869091B1
公开(公告)日：2005-03-22
申请号：US09707450
申请日：2000-11-07
申请人： Gerald D. Anderson , Michael W. Mattice , John M. Khoury , Thomas M. Drouillard , Kermit G. Rowe, III , David I. Fretwell , Alistair B. Lovett
发明人： Gerald D. Anderson , Michael W. Mattice , John M. Khoury , Thomas M. Drouillard , Kermit G. Rowe, III , David I. Fretwell , Alistair B. Lovett
IPC分类号： B60G7/00 , B60G21/055 , B60G9/00
CPC分类号： B60G21/0551 , B60G7/001 , B60G21/055 , B60G2200/20 , B60G2204/1222 , B60G2204/44 , B60G2204/45 , B60G2206/012 , B60G2206/013 , B60G2206/427 , B60G2206/70 , B60G2206/8103 , B60G2206/8112 , Y10T29/49622
摘要： A method for enhancing the physical characteristics of a localized area of a suspension component by adding material to the points of high stress without a significant increase in weight or diameter of the suspension component. The material is in the form of a sleeve added to the exterior surface of the suspension component, a core added to the interior surface of a tubular suspension component, winding filaments, or powered material.
摘要翻译：通过向高应力点添加材料而不显着增加悬浮组分的重量或直径来增强悬浮组分的局部区域的物理特性的方法。该材料是加到悬挂部件的外表面上的套筒的形式，一个核心被添加到管状悬挂部件的内表面，缠绕细丝或动力材料。

6. 发明授权

US06384388B1 Method of enhancing the bending process of a stabilizer bar 失效
标题翻译：增强稳定杆弯曲过程的方法
公开(公告)号：US06384388B1
公开(公告)日：2002-05-07
申请号：US09715598
申请日：2000-11-17
申请人： Gerald D. Anderson , John M. Khoury , Michael W. Mattice , Thomas M. Drouillard , Kermit G. Rowe, III , David Ian Fretwell , Alistair Bruce Christian Lovatt
发明人： Gerald D. Anderson , John M. Khoury , Michael W. Mattice , Thomas M. Drouillard , Kermit G. Rowe, III , David Ian Fretwell , Alistair Bruce Christian Lovatt
IPC分类号： H05B610
CPC分类号： B60G21/055 , B60G2206/427 , B60G2206/81 , B60G2206/8103 , B60G2206/81035
摘要： A method of enhancing the bending process of a stabilizer bar by locally pre-heating the stabilizer bar immediately prior to formation. By pre-heating the stabilizer bar, the stress in the stabilizer bar is relieved at the bending areas. This allows larger bars to be formed which would otherwise be outside of machine parameters. In the disclosed embodiments, the stabilizer bar is locally heated by induction coils or resistance heating at the bend areas.
摘要翻译：一种通过在形成之前立即预热稳定杆来增强稳定杆弯曲过程的方法。通过预热稳定杆，稳定杆中的应力在弯曲区域被释放。这允许形成更大的条，否则这些条不在机器参数之外。在所公开的实施例中，稳定杆通过感应线圈或弯曲区域的电阻加热局部加热。

7. 发明授权

US5327302A Data filter tuning for constant density recording applications 失效
标题翻译：用于恒定密度记录应用的数据滤波器调谐
公开(公告)号：US5327302A
公开(公告)日：1994-07-05
申请号：US943337
申请日：1992-09-16
申请人： John M. Khoury , Dale H. Nelson
发明人： John M. Khoury , Dale H. Nelson
IPC分类号： G11B20/14 , G11B19/28 , G11B20/10 , H03H11/12 , H03L7/06 , G11B5/035 , G11B5/09
CPC分类号： H03H11/1291 , G11B20/10
摘要： An arrangement for tuning a data filter in a mass storage system. The filter cutoff frequency (low pass) may be set as a percentage above or below the incoming data rate to achieve the desired "eye opening" in read data. The frequency of a reference oscillator in a phase-locked-loop (PLL) and the cutoff frequency of the filter is controlled by a common control signal from the PLL. The PLL, locked to a scaled multiple of the data rate, determines the cutoff frequency of the filter.
摘要翻译：用于调整大容量存储系统中的数据滤波器的装置。滤波器截止频率（低通）可以设置为高于或低于输入数据速率的百分比，以在读取数据中实现所需的“开眼”。锁相环（PLL）中的参考振荡器的频率和滤波器的截止频率由PLL的公共控制信号控制。锁定到数据速率的缩放倍数的PLL确定滤波器的截止频率。

8. 发明授权

US08493146B2 Amplifier using fast discharging reference 有权
标题翻译：放大器采用快速放电参考
公开(公告)号：US08493146B2
公开(公告)日：2013-07-23
申请号：US13045233
申请日：2011-03-10
申请人： Pavel Konecny , Jinwen Xiao , John M. Khoury
发明人： Pavel Konecny , Jinwen Xiao , John M. Khoury
IPC分类号： H03F3/217
CPC分类号： H03K7/08 , H03F3/2173 , H03K17/166 , H03K2217/0027 , H03K2217/0045
摘要： Techniques are disclosed relating to charging and discharging a gate of transistor. In one embodiment, an apparatus is disclosed that includes a driver configured to discharge a gate of a transistor. The driver is configured to discharge the gate at a first rate until reaching a Miller plateau for the transistor, and to discharge the gate at a second rate after reaching the Miller plateau. In such an embodiment, the first rate is greater than the second rate. In some embodiments, the driver is also configured to charge the gate of the transistor at a third rate until reaching a Miller plateau for the transistor, and to charge the gate at a fourth rate after reaching the Miller plateau, the third rate being greater than the fourth rate. In some embodiments, the apparatus is a class D amplifier.
摘要翻译：公开了关于对晶体管的栅极进行充电和放电的技术。在一个实施例中，公开了一种装置，其包括被配置为对晶体管的栅极进行放电的驱动器。驱动器被配置为以第一速率排放门，直到达到晶体管的Miller平台，并且在达到Miller平台之后以第二速率排出门。在这种实施例中，第一速率大于第二速率。在一些实施例中，驱动器还被配置为以三速对晶体管的栅极充电，直到达到晶体管的Miller平台为止，并且在达到Miller平台之后以第四速率对栅极充电，第三速率大于第四率。在一些实施例中，该装置是D类放大器。

9. 发明授权

US08446186B2 Time-shared latency locked loop circuit for driving a buffer circuit 有权
标题翻译：用于驱动缓冲电路的时间共享延迟锁定环路
公开(公告)号：US08446186B2
公开(公告)日：2013-05-21
申请号：US12795612
申请日：2010-06-07
申请人： John M. Khoury , Eduardo Viegas
发明人： John M. Khoury , Eduardo Viegas
IPC分类号： H03L7/00
CPC分类号： H03L7/0818
摘要： In an embodiment, a device includes a buffer circuit with first and second buffer outputs and a latency locked loop (LLL) circuit. The LLL circuit includes first and second LLL inputs for receiving first and second input signals and includes at least one shared component that is time shared. The at least one shared component is configured to measure edge timing errors in output signals on the first and second buffer outputs relative to the first and second inputs signals and to generate delay adjustment signals to adjust timing of edge transitions within the first and second input signals provided to the buffer circuit to control a total propagation delay from the first and second LLL inputs to the first and second buffer outputs.
摘要翻译：在一个实施例中，设备包括具有第一和第二缓冲器输出的缓冲器电路和等待时间锁定环路（LLL）电路。 LLL电路包括用于接收第一和第二输入信号的第一和第二LLL输入，并且包括时间共享的至少一个共享组件。所述至少一个共享组件被配置为测量相对于第一和第二输入信号的第一和第二缓冲器输出上的输出信号中的边缘定时误差，并且产生延迟调整信号以调整第一和第二输入信号内的边沿转换的定时提供给缓冲电路以控制从第一和第二LLL输入到第一和第二缓冲器输出的总传播延迟。

10. 发明申请

US20110298509A1 TIME-SHARED LATENCY LOCKED LOOP CIRCUIT FOR DRIVING A BUFFER CIRCUIT 有权
标题翻译：用于驱动缓冲电路的时间较短的锁定环路电路
公开(公告)号：US20110298509A1
公开(公告)日：2011-12-08
申请号：US12795612
申请日：2010-06-07
申请人： John M. Khoury , Eduardo Viegas
发明人： John M. Khoury , Eduardo Viegas
IPC分类号： H03L7/06
CPC分类号： H03L7/0818
摘要： In an embodiment, a device includes a buffer circuit with first and second buffer outputs and a latency locked loop (LLL) circuit. The LLL circuit includes first and second LLL inputs for receiving first and second input signals and includes at least one shared component that is time shared. The at least one shared component is configured to measure edge timing errors in output signals on the first and second buffer outputs relative to the first and second inputs signals and to generate delay adjustment signals to adjust timing of edge transitions within the first and second input signals provided to the buffer circuit to control a total propagation delay from the first and second LLL inputs to the first and second buffer outputs.
摘要翻译：在一个实施例中，设备包括具有第一和第二缓冲器输出的缓冲器电路和等待时间锁定环路（LLL）电路。 LLL电路包括用于接收第一和第二输入信号的第一和第二LLL输入，并且包括时间共享的至少一个共享组件。所述至少一个共享组件被配置为测量相对于第一和第二输入信号的第一和第二缓冲器输出上的输出信号中的边缘定时误差，并且产生延迟调整信号以调整第一和第二输入信号内的边沿转换的定时提供给缓冲电路以控制从第一和第二LLL输入到第一和第二缓冲器输出的总传播延迟。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式