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1. 发明授权

US07991296B1 Method and apparatus for data frame synchronization and delineation 有权
标题翻译：用于数据帧同步和描绘的方法和装置
公开(公告)号：US07991296B1
公开(公告)日：2011-08-02
申请号：US11938019
申请日：2007-11-09
申请人： Cesar A. Johnston , John M. Chiang
发明人： Cesar A. Johnston , John M. Chiang
IPC分类号： H04B10/00 , H04J14/00
CPC分类号： H04J3/0608
摘要： A circuit and method to synchronize with a data transmission having a plurality of data transmission frames each with a start boundary identified by a predetermined synchronization pattern, includes comparing sets of data within the data transmission to a predetermined synchronization pattern. A frame tracking signal is assigned to each one of the plurality of comparison results that indicates a match between a data pattern within one of the plurality of sets of data and the predetermined synchronization pattern, including matches that occur multiple times within a known duration of the data transmission frame duration. Based on each frame tracking signal assigned to a comparison result, the start boundary of the data transmission frames is searched. The start boundary may be search by monitoring successive occurrences of the predetermined synchronization pattern in the data transmission at intervals of the known data transmission frame duration for each data matching data pattern. If the predetermined synchronization pattern occurs successively in the data transmission, the associated data pattern is confirmed as the synchronization pattern in the data transmission, and synchronization with the data transmission is achieved.
摘要翻译：一种与具有多个数据传输帧的数据传输同步的电路和方法，每个数据传输帧具有由预定的同步模式识别的起始边界，包括将数据传输中的数据集合与预定的同步模式进行比较。帧跟踪信号被分配给多个比较结果中的每一个，其指示多个数据集合中的一个数据和预定同步模式之间的数据模式之间的匹配，包括在所述多个比较结果的已知持续时间内发生多次的匹配数据传输帧持续时间。基于分配给比较结果的每个帧跟踪信号，搜索数据传输帧的起始边界。可以通过以每个数据匹配数据模式的已知数据传输帧持续时间的间隔监视数据传输中的预定同步模式的连续出现来搜索起始边界。如果在数据传输中连续发生预定同步模式，则在数据传输中确认相关联的数据模式作为同步模式，并实现与数据传输的同步。

2. 发明授权

US06813266B1 Pipelined access to address table in a network switch 有权
标题翻译：流水线访问网络交换机中的地址表
公开(公告)号：US06813266B1
公开(公告)日：2004-11-02
申请号：US09315851
申请日：1999-05-21
申请人： John M. Chiang , Shashank Merchant
发明人： John M. Chiang , Shashank Merchant
IPC分类号： H04L1228
CPC分类号： H04L12/5601 , H04L49/108 , H04L2012/5624 , H04L2012/5652 , H04L2012/5679 , H04L2012/568 , H04L2012/5681
摘要： A network switch configured for switching data packets across multiple ports uses decision making logic to generate frame forwarding information. The decision making logic employs a pipelined architecture that enables multiple data frames to be processed simultaneously to increase data throughput. The decision making logic also pipelines access to an address lookup table that stores the data forwarding information. An arbitration circuit provides the decision making device with automatic access to the address table in alternate time slots and also enables other circuits to access the address table in predetermined time slots.
摘要翻译：配置为跨多个端口切换数据包的网络交换机使用决策逻辑生成帧转发信息。决策逻辑采用流水线架构，可以同时处理多个数据帧，从而提高数据吞吐量。决策逻辑还可以访问存储数据转发信息的地址查找表。仲裁电路为决策设备提供在备用时隙中对地址表的自动访问，并且使得其他电路能够在预定时隙中访问地址表。

3. 发明授权

US06501734B1 Apparatus and method in a network switch for dynamically assigning memory interface slots between gigabit port and expansion port 有权
标题翻译：网络交换机中的装置和方法，用于在千兆端口和扩展端口之间动态分配存储器接口槽
公开(公告)号：US06501734B1
公开(公告)日：2002-12-31
申请号：US09317150
申请日：1999-05-24
申请人： Ching Yu , Xiaohua Zhuang , Bahadir Erimli , John M. Chiang , Shashank Merchant , Robert Williams , Edward Yang , Chandan Egbert , Vallath Nandakumar , Ian Lam , Eric Tsin-Ho Leung
发明人： Ching Yu , Xiaohua Zhuang , Bahadir Erimli , John M. Chiang , Shashank Merchant , Robert Williams , Edward Yang , Chandan Egbert , Vallath Nandakumar , Ian Lam , Eric Tsin-Ho Leung
IPC分类号： H04J116
CPC分类号： H04L49/103 , H04L49/254 , H04L49/3027 , H04L49/351 , H04L49/352 , H04L49/354 , H04L49/90 , H04L49/901
摘要： A network switch having switch ports for full-duplex communication of data packets with respective network nodes according to Ethernet (IEEE 802.3) protocol dynamically allocates external memory bandwidth slots between high data rate ports. An external memory interface determines if a high data rate port makes a request for a bandwidth slot and grants the request if made. The slot is taken from a selected group which is a subset of the total number of slots. If a request for the slot is not made, the external memory interface assigns the slot to another high data rate port. Lower data rate ports in the network switch are assigned fixed slots from those slots not from within the selected group of slots. The dynamic allocation of bandwidth slots between the high data rate port enables the efficient use of limited memory bandwidth resources.
摘要翻译：具有根据以太网（IEEE 802.3）协议的具有各个网络节点的数据分组全双工通信的交换机端口的网络交换机动态地在高数据速率端口之间分配外部存储器带宽时隙。外部存储器接口确定高数据速率端口是否对带宽槽进行请求，如果发出请求则确定该请求。时隙是从所选择的组中获取的，该组是总时隙数的子集。如果没有对插槽进行请求，则外部存储器接口将插槽分配给另一个高数据速率端口。网络交换机中的较低数据速率端口从这些时隙中分配固定时隙，而不是在所选择的时隙组内。高数据速率端口之间的带宽时隙的动态分配使得能够有效地利用有限的存储器带宽资源。

4. 发明授权

US06445709B1 Method and apparatus for finding a match entry using receive port number embedded in the port vector 有权
标题翻译：使用嵌入在端口向量中的接收端口号来找到匹配条目的方法和装置
公开(公告)号：US06445709B1
公开(公告)日：2002-09-03
申请号：US09311367
申请日：1999-05-13
申请人： John M. Chiang
发明人： John M. Chiang
IPC分类号： H04L1256
CPC分类号： H04L49/354 , H04L12/4645 , H04L12/467 , H04L49/205 , H04L49/3009 , H04L49/3027 , H04L49/351
摘要： A network switch configured for switching data packets across multiple ports uses an address table to generated frame forwarding information. The switch receives frame information including a source address and destination address along with a virtual local area network (VLAN) ID, if applicable. A decision-making engine searches a network address table to “learn” Medium Access Control (MAC) addresses without having to store receive port numbers by embedding the receive port number in the stored port vector fields.
摘要翻译：配置为跨多个端口切换数据包的网络交换机使用地址表来生成帧转发信息。如果适用，交换机接收包括源地址和目的地址以及虚拟局域网（VLAN）ID的帧信息。决策引擎搜索网络地址表以“学习”媒体访问控制（MAC）地址，而不必通过将接收端口号嵌入存储的端口向量域中来存储接收端口号。

5. 发明授权

US09178713B1 Optical line termination in a passive optical network 有权
标题翻译：无源光网络中的光线路终端
公开(公告)号：US09178713B1
公开(公告)日：2015-11-03
申请号：US11937396
申请日：2007-11-08
申请人： Cesar A. Johnston , John M. Chiang
发明人： Cesar A. Johnston , John M. Chiang
IPC分类号： H04L12/28 , H04L7/00 , H04J3/16 , H04J14/00
CPC分类号： H04L12/2898 , H04J3/1652 , H04L7/0075 , H04L12/2861 , H04Q11/0067 , H04Q2011/0064
摘要： In a line termination unit integrated circuit in a point-to-multipoint network, a receiver receives an upstream transmission from a network termination unit within the point-to-multipoint network, a transmitter transmits a downstream transmission to a network termination unit within the point-to-multipoint network, and an internal processor operatively coupled to the receiver processes sub-fields within the overhead field of the upstream transmission. The internal processor is also operatively coupled to the transmitter to assemble the overhead field of the downstream transmission. The upstream transmission is an upstream transmission convergence frame format having an overhead field and a payload field, and the downstream transmission is a downstream transmission convergence frame format having an overhead field and a payload field.
摘要翻译：在点对多点网络中的线路终端单元集成电路中，接收机从点对多点网络中的网络终端单元接收上行传输，发射机向所述点到多点网络内的网络终端单元发送下行传输以及可操作地耦合到所述接收机的内部处理器处理所述上行传输的开销字段内的子域。内部处理器也可操作地耦合到发射器以组装下游传输的开销字段。上行传输是具有开销字段和有效载荷字段的上行传输会聚帧格式，下行传输是具有开销字段和有效载荷字段的下行传输会聚帧格式。

6. 发明授权

US08582707B2 Programmable universal asynchronous receiver/transmitter (UART) based on reference frequency 失效
标题翻译：基于参考频率的可编程通用异步收发器（UART）
公开(公告)号：US08582707B2
公开(公告)日：2013-11-12
申请号：US12877823
申请日：2010-09-08
申请人： John M. Chiang
发明人： John M. Chiang
IPC分类号： H04L7/00
CPC分类号： H04L7/08 , H04L7/10 , H04L25/0262
摘要： In one embodiment, a method includes determining pre-calculated information. The pre-calculated information is used to determine a counter pattern for a reference clock. The counter pattern include, for at least one data bit, a number of reference clock cycles of the reference clock that is determined based on a frequency of the reference clock and a data rate of a serial data stream. The serial data stream is sampled to read a plurality of data bits based on the counter pattern. A data bit is sampled based on the number of reference clock cycles associated with the data bit.
摘要翻译：在一个实施例中，一种方法包括确定预先计算的信息。预先计算的信息用于确定参考时钟的计数器模式。对于至少一个数据位，计数器模式包括基于参考时钟的频率和串行数据流的数据速率确定的参考时钟的参考时钟周期的数量。对串行数据流进行采样，以便根据计数器模式读取多个数据位。基于与数据位相关联的参考时钟周期的数量对数据位进行采样。

7. 发明授权

US08326938B1 Packet buffer apparatus and method 有权
标题翻译：分组缓冲装置和方法
公开(公告)号：US08326938B1
公开(公告)日：2012-12-04
申请号：US13228936
申请日：2011-09-09
申请人： John M. Chiang , Cesar A. Johnston
发明人： John M. Chiang , Cesar A. Johnston
IPC分类号： G06F15/167
CPC分类号： H01M4/92 , H01M4/925 , H01M4/926 , H01M2008/1095
摘要： An apparatus including a first memory, a second memory, and a direct memory access engine. The first memory stores one or more packet descriptors. The second memory stores one or more packets for transmission via a communication link. The direct memory access engine is configured to i) determine when the one or more packet descriptors have been written, by a host, to the first memory, ii) read the one or more packet descriptors from the first memory in response to determining that the one or more packet descriptors have been written to the first memory by the host, iii) determine, using the one or more packet descriptors, one or more respective locations of one or more packets in a host memory, and iv) initiate a direct memory access transfer of the one or more packets from the one or more respective locations in the host memory to the second memory.
摘要翻译：一种包括第一存储器，第二存储器和直接存储器存取引擎的装置。第一存储器存储一个或多个分组描述符。第二存储器存储用于经由通信链路传输的一个或多个分组。直接存储器访问引擎被配置为i）确定一个或多个分组描述符何时被主机写入到第一存储器，ii）响应于确定所述第一存储器读取所述一个或多个分组描述符，一个或多个分组描述符已被主机写入第一存储器，iii）使用一个或多个分组描述符确定主机存储器中的一个或多个分组的一个或多个相应位置，以及iv）发起直接存储器将一个或多个分组从主机存储器中的一个或多个相应位置的访问传输到第二存储器。

8. 发明授权

US07818389B1 Packet buffer apparatus and method 有权
标题翻译：分组缓冲装置和方法
公开(公告)号：US07818389B1
公开(公告)日：2010-10-19
申请号：US11948753
申请日：2007-11-30
申请人： John M. Chiang , Cesar A. Johnston
发明人： John M. Chiang , Cesar A. Johnston
IPC分类号： G06F15/167
CPC分类号： H01M4/92 , H01M4/925 , H01M4/926 , H01M2008/1095
摘要： In managing and buffering packet data for transmission out of a host, descriptor ring data is pushed in from a host memory into a descriptor ring cache and cached therein. The descriptor ring data is processed to read a data packet descriptor, and a direct memory access is initiated to the host to read the data packet corresponding to the read data packet descriptor to a data transmission buffer. The data packet is written by the direct memory access into the data transmission buffer and cached therein. A return pointer is written to the host memory by the direct memory access indicating that the data packet descriptor has been read and the corresponding data packet has been transmitted. In managing and buffering packet data for transmission to a host, descriptor ring data is pushed in from a host memory into a descriptor ring cache and cached therein. Data packets for transmission to the host memory are received and cached in a data reception buffer. Data is read from the data reception buffer according to a data packet descriptor retrieved from the descriptor ring cache, and the data packet is written to a data reception queue within the host memory by a direct memory access. A return pointer is written to the host memory by the direct memory access indicating that the data packet has been written.
摘要翻译：在管理和缓存用于从主机发送的分组数据时，将描述符环数据从主机存储器推入描述符环形缓存并缓存在其中。处理描述符环数据以读取数据分组描述符，并且向主机发起直接存储器访问以将对应于读取数据分组描述符的数据分组读取到数据传输缓冲器。数据包通过直接存储器访问写入数据传输缓冲器并缓存在其中。通过直接存储器访问将返回指针写入主机存储器，指示已经读取数据分组描述符并且已经发送了相应的数据分组。在管理和缓冲分组数据以传输到主机时，将描述符环数据从主机存储器推入描述符环缓存并缓存在其中。用于发送到主机存储器的数据分组被接收并缓存在数据接收缓冲器中。从数据接收缓冲器根据从描述符环形高速缓存检索的数据包描述符读取数据，并通过直接存储器访问将数据包写入主机存储器内的数据接收队列。通过直接存储器访问将返回指针写入主机存储器，指示数据包已被写入。

9. 发明授权

US06658015B1 Multiport switch with plurality of logic engines for simultaneously processing different respective data frames 失效
标题翻译：具有多个逻辑引擎的多端口交换机，用于同时处理不同的相应数据帧
公开(公告)号：US06658015B1
公开(公告)日：2003-12-02
申请号：US09321623
申请日：1999-05-28
申请人： Shashank Merchant , Chandan Egbert , John M. Chiang
发明人： Shashank Merchant , Chandan Egbert , John M. Chiang
IPC分类号： H04L1256
CPC分类号： H04L49/103 , H04L49/3027 , H04L49/354 , H04L49/90
摘要： A network switch configured for switching data packets across multiple ports uses decision making device to generate frame forwarding information. The decision making device employs a modular architecture that enables data frames to be processed simultaneously and increase data throughput. The decision making device also includes a memory to store frame headers to minimize the signaling between the decision making device and the receive devices.
摘要翻译：配置为跨多个端口切换数据包的网络交换机使用决策设备生成帧转发信息。决策设备采用模块化架构，可以同时处理数据帧并提高数据吞吐量。决策设备还包括存储器以存储帧头以最小化决策设备和接收设备之间的信令。

10. 发明授权

US06442137B1 Apparatus and method in a network switch for swapping memory access slots between gigabit port and expansion port 失效
标题翻译：用于交换千兆端口和扩展端口之间的存储器访问槽的网络交换机中的装置和方法
公开(公告)号：US06442137B1
公开(公告)日：2002-08-27
申请号：US09317143
申请日：1999-05-24
申请人： Ching Yu , Xiaohua Zhuang , Bahadir Erimli , John M. Chiang , Shashank Merchant , Robert Williams , Edward Yang , Chandan Egbert , Vallath Nandakumar , Ian Lam , Eric Tsin-Ho Leung
发明人： Ching Yu , Xiaohua Zhuang , Bahadir Erimli , John M. Chiang , Shashank Merchant , Robert Williams , Edward Yang , Chandan Egbert , Vallath Nandakumar , Ian Lam , Eric Tsin-Ho Leung
IPC分类号： H04L522
CPC分类号： H04L49/901 , H04L49/103 , H04L49/3027 , H04L49/351 , H04L49/352 , H04L49/90 , H04L49/9031 , H04L49/9078
摘要： A network switch having switch ports for full-duplex communication of data packets with respective network nodes according to Ethernet (IEEE 802.3) protocol that allocates a prescribed number of external memory bandwidth slots between high data rate ports based on the compared amount of network traffic on the respective ports. A scheduler within an external memory interface initially assigns memory access slots to the respective high data rate ports according to a prescribed sequence. If the scheduler subsequently detects that the network data traffic on a port having less slots is higher than the traffic on a port having more slots, the slots are swapped between the high data rate ports. Additionally, a clock multiplexer in one of the high data rate ports adjusts the data rate of the port dependent upon the number of slots assigned to that port. The swapping of bandwidth slots between the high data rate ports along with the adjustment of the port clock rate enables the efficient use of limited memory bandwidth resources.
摘要翻译：网络交换机具有用于根据以太网（IEEE 802.3）协议的具有各网络节点的数据分组全双工通信的交换机端口，该协议基于网络流量的比较量在高数据速率端口之间分配规定数量的外部存储器带宽时隙各个端口。外部存储器接口中的调度器根据规定的顺序，初始地将存储器访问时隙分配给相应的高数据速率端口。如果调度器随后检测到具有较少时隙的端口上的网络数据流量高于具有更多时隙的端口上的流量，则这些时隙在高数据速率端口之间交换。此外，高数据速率端口之一中的时钟多路复用器根据分配给该端口的时隙数来调整端口的数据速率。在高数据速率端口之间交换带宽时隙以及端口时钟速率的调整使得能够有效地使用有限的存储器带宽资源。

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