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1. 发明申请

WO2002087116A1 SYSTEM AND METHOD FOR EMBEDDING CONTROL INFORMATION WITHIN AN OPTICAL WIRELESS LINK 审中-公开
标题翻译：用于在光纤无线链路中嵌入控制信息的系统和方法
公开(公告)号：WO2002087116A1
公开(公告)日：2002-10-31
申请号：PCT/US2002/012530
申请日：2002-04-19
申请人： TEXAS INSTRUMENTS INCORPORATED , CHRISTIANSEN, Grant , NORTHRUP, Karl, Kirk , KELLER, Robert, Clair , MELENDEZ, Jose, Luis , SO, John, Ling, Wing
发明人： CHRISTIANSEN, Grant , NORTHRUP, Karl, Kirk , KELLER, Robert, Clair , MELENDEZ, Jose, Luis , SO, John, Ling, Wing
IPC分类号： H04B10/00
CPC分类号： H04B10/1121 , H04B10/1123 , H04B10/1125 , H04B10/1149 , H04B10/2587
摘要： Optical wireless links (4, 6) communicate beam alignment information between them over a collimated, modulated light beam, without the requirement of a secondary channel. The alignment feedback signal (16, 18, 20, 22) can be formatted as control packets that are inserted between data packets traveling over the optical wireless channel, as control packets that are combined with the data packets, as a low frequency modulation of the light beam, or similar approaches. Alignment feedback signals are used by the device receiving the signal to align its light beam using a beam steering device, such as a micro-mirror device. Control signals preferably include x and y coordinate informaiton relating to the position of both devices that are communicating, as well as time stamp, sample number, and similar synchronization information. Control packets are extracted from the data stream by a switch based upon the destination address of the control packets.
摘要翻译：光无线链路（4,6）在准直的调制光束之间在它们之间传送光束对准信息，而不需要辅助信道。对准反馈信号（16,18,20,22）可以被格式化为在作为与数据分组组合的控制分组时插入在光无线信道上行进的数据分组之间的控制分组，作为低频调制光束或类似的方法。接收信号的装置使用对准反馈信号，以使用诸如微镜装置的光束转向装置对准其光束。控制信号优选地包括与正在通信的两个设备的位置相关的x和y坐标信息，以及时间戳，采样号和类似的同步信息。基于控制分组的目的地地址，交换机从数据流中提取控制分组。

2. 发明授权

US07506359B1 Method for preventing parasitic usage of web page embedded files 失效
标题翻译：防止网页嵌入文件寄生使用的方法
公开(公告)号：US07506359B1
公开(公告)日：2009-03-17
申请号：US09667366
申请日：2000-09-22
申请人： Christopher John Ling
发明人： Christopher John Ling
IPC分类号： G06F7/04 , G06F17/30 , H04L9/32
CPC分类号： G06F21/128
摘要： A request is received from a client for a web page hosted by a web server. Responsive to this request, a persistent client state object having an identifier therein is returned to the client. When a request is received from a client for elements of the web page hosted by the web server, the client is first required to return the persistent client state object having the identifier therein before the requested web page element is sent to the client.
摘要翻译：从客户端收到由Web服务器托管的网页的请求。响应于该请求，具有其中的标识符的持久客户端状态对象被返回给客户端。当从客户机接收到由Web服务器托管的网页的元素的请求时，首先要求客户端在请求的网页元素被发送到客户端之前返回具有标识符的持久客户端状态对象。

3. 发明授权

US06965470B2 Adaptive control of power transients 失效
标题翻译：电力瞬变的自适应控制
公开(公告)号：US06965470B2
公开(公告)日：2005-11-15
申请号：US10224203
申请日：2002-08-20
申请人： John Ling Wing So
发明人： John Ling Wing So
IPC分类号： G02B6/34 , G02B6/35 , H04B10/18 , H01S3/00
CPC分类号： H04B10/25133 , G02B6/2706 , G02B6/278 , G02B6/2793 , G02B6/2931 , G02B6/29313 , G02B6/29391 , G02B6/29394 , G02B6/29395 , G02B6/3512 , G02B6/356 , G02B6/3588
摘要： Power transient control in an optical network by power measurement and prediction with a simple-to-compute model to drive an optical filter control.
摘要翻译：通过功率测量和预测，通过简单的计算模型驱动光学滤波器控制，在光网络中进行功率瞬态控制。

4. 发明授权

US06842549B2 Optical system and method 有权
标题翻译：光学系统和方法
公开(公告)号：US06842549B2
公开(公告)日：2005-01-11
申请号：US10224146
申请日：2002-08-20
申请人： John Ling Wing So
发明人： John Ling Wing So
IPC分类号： G02B5/20 , G02B6/34 , G02B6/35 , G02B26/08 , H04B10/17 , G02B6/26
CPC分类号： G02B6/2931 , G02B5/203 , G02B6/2706 , G02B6/278 , G02B6/2793 , G02B6/29313 , G02B6/29389 , G02B6/29391 , G02B6/29394 , G02B6/29395 , G02B6/3512 , G02B6/356 , G02B6/3588 , G02B26/0841 , H04B10/2941
摘要： Adaptive dynamic optical filters with wavelength spreading onto a micromirror array and re-configurable attenuation according to measured intensity as a function of wavelength.
摘要翻译：自适应动态光学滤波器，其波长扩展到微镜阵列上，并根据测量的强度作为波长的函数重新配置衰减。

5. 发明授权

US06179489B2 Devices, methods, systems and software products for coordination of computer main microprocessor and second microprocessor coupled thereto 失效
标题翻译：用于协调计算机主微处理器和与其耦合的第二微处理器的装置，方法，系统和软件产品
公开(公告)号：US06179489B2
公开(公告)日：2001-01-30
申请号：US08833267
申请日：1997-04-04
申请人： John Ling Wing So , Jeffrey L. Kerr , Steven R. Magee , Jun Tang
发明人： John Ling Wing So , Jeffrey L. Kerr , Steven R. Magee , Jun Tang
IPC分类号： G06F1300
CPC分类号： G06F9/5044 , G06F9/544 , G06F9/545 , G06F2209/509
摘要： A process is provided for operating a computer system (100) having a storage holding an operating system (OS) and an application program (APP.exe) and a third program (VSP Kernel), a first processor (106) having an instruction set, and a second processor (1730) having a different instruction set. The process includes a first step of running the first processor (106) to determine whether a part of the application shall be run on the first processor or the second processor and then establishing a second processor object (VSP OBJECT1) if said part shall be run on the second processor and the first processor (106) sending a message that the second processor (1730) is to run said at least part of the application program. The third program establishes message handling functions and bus masters data transfer operations for the second processor between the host running the operating system and the second processor running the third program. The process concurrently runs the second processor to perform operations defined by the third program, including to access memory to detect the message that the second processor is to run said at least part of the application program, and runs the second processor (1730) to access the second processor object and thereby determine operations for the second processor to access second processor instructions for said part of the application program and data to be processed according to said second processor instructions.
摘要翻译：提供一种用于操作具有存储操作系统（OS）和应用程序（APP.exe）和第三程序（VSP内核）的存储器的计算机系统（100）的过程，具有指令集的第一处理器（106），以及具有不同指令集的第二处理器（1730）。该过程包括运行第一处理器（106）以确定应用程序的一部分是否应在第一处理器或第二处理器上运行并且然后建立第二处理器对象（VSP OBJECT1）的第一步骤，如果所述部分将被运行在第二处理器和第一处理器（106）上发送第二处理器（1730）要运行所述应用程序的至少一部分的消息。第三程序在运行操作系统的主机和运行第三程序的第二处理器之间建立第二处理器的消息处理功能和总线主机数据传输操作。该过程同时运行第二处理器以执行由第三程序定义的操作，包括访问存储器以检测第二处理器要运行所述应用程序的至少一部分的消息，并运行第二处理器（1730）以访问第二处理器对象，从而确定第二处理器根据所述第二处理器指令访问应用程序的所述部分的第二处理器指令和要处理的数据的操作。

6. 发明授权

US6148389A PC circuits, systems and methods 有权
标题翻译： PC电路，系统和方法
公开(公告)号：US6148389A
公开(公告)日：2000-11-14
申请号：US372457
申请日：1999-08-11
申请人： John Ling Wing So
发明人： John Ling Wing So
IPC分类号： G06F9/38 , G06F9/50 , G06F13/28 , G06F13/40 , G06F9/44
CPC分类号： G06F9/50 , G06F13/28 , G06F13/4018 , G06F13/4027 , G06F9/3879
摘要： An improved PC system that includes a main CPU microprocessor, a file-based operating system, and a DSP microprocessor arranged so that the DSP can execute main CPU operations during time intervals in which the main CPU is otherwise occupied, thereby increasing the bandwidth of the system is provided. This PC system may include multiple CPUs and/or multiple DSPs.
摘要翻译：一种改进的PC系统，其包括主CPU微处理器，基于文件的操作系统和DSP微处理器，其被布置为使得DSP可以在主CPU另外被占用的时间间隔期间执行主CPU操作，从而增加系统。该PC系统可以包括多个CPU和/或多个DSP。

7. 发明授权

US6105119A Data transfer circuitry, DSP wrapper circuitry and improved processor devices, methods and systems 失效
标题翻译：数据传输电路，DSP封装电路和改进的处理器设备，方法和系统
公开(公告)号：US6105119A
公开(公告)日：2000-08-15
申请号：US833153
申请日：1997-04-04
申请人： Jeffrey L. Kerr , John Ling Wing So , Steven R. Magee
发明人： Jeffrey L. Kerr , John Ling Wing So , Steven R. Magee
IPC分类号： G06F13/40 , G06F12/00
CPC分类号： G06F13/4027
摘要： An integrated circuit (1720) includes a dual-port memory (3330.1) having a first memory port (Port A) and a second memory port (Port B), a bus interface block (5010) including bus master (5016) and bus slave circuitry (5018), and a byte-channeling block (5310) coupled between the first memory port (Port A) and the bus interface block (5010) operable to convert non-aligned data addresses into aligned data. Advantageously, this invention includes a single bus master serving all application hardware. This relieves the host of the extra burden of communicating to slave circuits, reducing host I/O MIPS significantly. The digital signal processor with an ASIC wrapper of this invention together provide super-bus-mastering to access the entire memory space in the system, including the entire virtual memory space accessible by the host processor. Other processes, systems, devices and methods are also disclosed.
摘要翻译：集成电路（1720）包括具有第一存储器端口（端口A）和第二存储器端口（端口B））的双端口存储器（3330.1），总线接口块（5010），包括总线主机（5016）和总线从设备电路（5018）和耦合在第一存储器端口（端口A）和总线接口块（5010）之间的字节通道块（5310），其可操作以将非对准的数据地址转换成对准的数据。有利地，本发明包括用于所有应用硬件的单总线主机。这减轻了主机与从属电路通信的额外负担，从而显着降低了主机I / O MIPS。具有本发明的ASIC封装器的数字信号处理器一起提供超级总线主控以访问系统中的整个存储器空间，包括由主机处理器可访问的整个虚拟存储器空间。还公开了其它过程，系统，设备和方法。

8. 发明授权

US5909559A Bus bridge device including data bus of first width for a first processor, memory controller, arbiter circuit and second processor having a different second data width 失效
标题翻译：总线桥接器件包括用于第一处理器的第一宽度的数据总线，存储器控制器，仲裁器电路和具有不同的第二数据宽度的第二处理器
公开(公告)号：US5909559A
公开(公告)日：1999-06-01
申请号：US832892
申请日：1997-04-04
申请人： John Ling Wing So
发明人： John Ling Wing So
IPC分类号： G06F13/40 , G06F13/00
CPC分类号： G06F13/4018
摘要： An integrated circuit (2210) provides on a single chip for use with a first processor (106) off-chip, the following combination: first terminals (of 2232) for first processor-related signals and defining a first data width (32-bit), second terminals for external bus-related signals (PCI), third terminals for memory-related signals (of 2258), and a DRAM memory controller (2250) connected to the third terminals. Further on chip is provided an arbiter circuit (2230), a bus bridge circuit (2236) coupled to the DRAM memory controller and to the second terminals, the bus bridge (2236) also coupled to the arbiter (2230), a second processor (2224) having a second data width (16-bit), and a bus interface circuit (2220) coupling the second data width of the second processor (2224) to the first data width. The bus interface circuit (2220) further has bus master and bus slave circuitry coupled between the second processor (2224) and the arbiter circuit (2230). The bus bridge (2236), the bus interface (2220) and the first terminals and the DRAM memory controller (2250) have datapaths selectively interconnected in response to the arbiter circuit (2230). Other devices, systems and methods are also disclosed.
摘要翻译：集成电路（2210）在单芯片上提供与芯片外的第一处理器（106）一起使用的以下组合：用于第一处理器相关信号的第一终端（2232），并且定义第一数据宽度（32位），用于外部总线相关信号（PCI）的第二终端，用于存储器相关信号的第二终端（2258）和连接到第三终端的DRAM存储器控制器（2250）。片上还提供了仲裁电路（2230），耦合到DRAM存储器控制器和第二终端的总线桥接电路（2236），还耦合到仲裁器（2230）的总线桥（2236），第二处理器 2224）和将第二处理器（2224）的第二数据宽度耦合到第一数据宽度的总线接口电路（2220）。总线接口电路（2220）还具有耦合在第二处理器（2224）和仲裁器电路（2230）之间的总线主机和总线从属电路。总线桥（2236），总线接口（2220）和第一端子和DRAM存储器控制器（2250）具有响应于仲裁器电路（2230）选择性地互连的数据路径。还公开了其他装置，系统和方法。

9. 发明申请

US20160015525A1 DYNAMIC FORCE GENERATION FOR BONE REPAIR 有权
标题翻译：动态生成骨修复
公开(公告)号：US20160015525A1
公开(公告)日：2016-01-21
申请号：US14771633
申请日：2014-03-03
申请人： Jeremy John LING
发明人： Jeremy John LING
IPC分类号： A61F2/44 , A61B17/70 , A61B17/80 , A61F2/28 , A61B17/72
CPC分类号： A61F2/4455 , A61B17/70 , A61B17/7016 , A61B17/72 , A61B17/7225 , A61B17/80 , A61B17/8004 , A61B17/866 , A61B2017/00876 , A61F2/28 , A61F2002/286 , A61F2002/30079 , A61F2002/30668
摘要： An orthopedic device delivers dynamic forces to a desired remote bone region. Dynamically arranged mechanical forces are known to stimulate bone cells (the process of mechanotransduction). The device includes an implantable element configured to couple with a generally accessible and healthy bone area, from which location it's configured to transmit forces to a remote bone area in need of repair, regrowth, or regeneration. Further, the device positions and orients the implantable element where it can be readily acted on by the device's force generator. The force generator is configured to impart dynamic forces that are transmitted through the implantable element and into a desired bone mass including a remote bone area in need of repair. This device promotes fracture healing, treats osteoporotic or other poor quality bone, and promotes vertebral fusion in conjunction with a spinal fusion procedure.
摘要翻译：整形外科设备将动力提供给所需的远端骨骼区域。已知动力排列的机械力刺激骨细胞（机械转导过程）。该装置包括可植入元件，该可植入元件被配置为与通常可接近和健康的骨骼区域联接，从该区域构造其将位置传递到需要修复，再生长或再生的远端骨骼区域。此外，该装置将可植入元件定位和定位，在该位置处可以容易地由该装置的力发生器作用。力产生器被配置成赋予通过可植入元件传递的动态力并进入包括需要修复的远侧骨区域的所需骨质量。该装置促进骨折愈合，治疗骨质疏松或其他质量差的骨，并且与脊柱融合术一起促进椎骨融合。

10. 发明申请

US20070036020A1 Bit-deskewing IO method and system 有权
标题翻译：位偏移IO方法和系统
公开(公告)号：US20070036020A1
公开(公告)日：2007-02-15
申请号：US11195082
申请日：2005-08-01
申请人： Edward Lee , Arvind Bomdica , Lin Chen , Claude Gauthier , Sam Huynh , Hiok-Tiaq Ng , John Ling , Jennifer Ho , Siji M.K. , Gin Yee , Joseph Macri
发明人： Edward Lee , Arvind Bomdica , Lin Chen , Claude Gauthier , Sam Huynh , Hiok-Tiaq Ng , John Ling , Jennifer Ho , Siji M.K. , Gin Yee , Joseph Macri
IPC分类号： G11C8/00
CPC分类号： H03L7/0814 , H03L7/07 , H03L7/0805 , H04L7/0004 , H04L7/0037 , H04L7/0337
摘要： An IO method and system for bit-deskewing are described. Embodiment includes a computer system with multiple components that transfer data among them. In one embodiment, a system component receives a forward strobe signal and multiple data bit signals from a transmitting component. The receiving component includes a forward strobe clock recovery circuit configurable to align a forward strobe sampling clock so as to improve sampling accuracy. The receiving component further includes at least one data bit clock recovery circuit configurable to align a data bit sampling clock so as to improve sampling accuracy, and to receive a signal from the forward strobe clock recovery circuit that causes the data bit sampling clock to track the forward strobe sampling clock during system operation.
摘要翻译：描述了用于位移校正的IO方法和系统。实施例包括具有在其间传送数据的多个组件的计算机系统。在一个实施例中，系统组件从发送组件接收正向选通信号和多个数据位信号。接收组件包括可选择对准前向选通采样时钟以提高采样精度的正向选通时钟恢复电路。接收组件还包括至少一个数据比特时钟恢复电路，可配置为对准数据比特采样时钟，以提高采样精度，并接收来自正向选通时钟恢复电路的信号，使得数据比特采样时钟跟踪系统运行期间的正向选通采样时钟。

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