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1. 发明申请

US20100097739A1 Capacitor Comprising Flex Crack Mitigation Voids 有权
标题翻译：电容器包括Flex裂纹缓解空隙
公开(公告)号：US20100097739A1
公开(公告)日：2010-04-22
申请号：US12253598
申请日：2008-10-17
申请人： John D. Prymak
发明人： John D. Prymak
IPC分类号： H01G4/30
CPC分类号： H01G4/30 , H01G4/12
摘要： A ceramic multilayer surface-mount capacitor with inherent crack mitigation void patterning to channel flex cracks into a safe zone, thereby negating any electrical failures.
摘要翻译：陶瓷多层表面贴装电容器具有固有的裂纹消除空间图案化，将柔性裂纹引导到安全区域，从而抵消任何电气故障。

2. 发明申请

US20100020473A1 SUBSTRATE WITH EMBEDDED PATTERNED CAPACITANCE 有权
标题翻译：具有嵌入式图形电容的基板
公开(公告)号：US20100020473A1
公开(公告)日：2010-01-28
申请号：US12180768
申请日：2008-07-28
申请人： John D. Prymak , Chris Stolarski , Alethia Melody , Antony P. Chacko , Gregory J. Dunn
发明人： John D. Prymak , Chris Stolarski , Alethia Melody , Antony P. Chacko , Gregory J. Dunn
IPC分类号： H01G9/15
CPC分类号： H05K1/162 , H01G9/012 , H01G9/042 , H01G9/045 , H01G9/15 , H05K3/429 , H05K2201/0329 , H05K2201/0355 , H05K2201/09509 , H05K2201/09763 , H05K2201/09909 , H05K2203/0315 , Y10T29/417 , Y10T29/435
摘要： A process for forming a laminate with capacitance and the laminate formed thereby. The process includes the steps of providing a substrate and laminating a conductive foil on the substrate wherein the foil has a dielectric. A conductive layer is formed on the dielectric. The conductive foil is treated to electrically isolate a region of conductive foil containing the conductive layer from additional conductive foil. A cathodic conductive couple is made between the conductive layer and a cathode trace and an anodic conductive couple is made between the conductive foil and an anode trace.
摘要翻译：一种用于形成具有电容的叠层的方法和由此形成的层压体。该方法包括以下步骤：提供衬底并将导电箔层压在衬底上，其中箔具有电介质。在电介质上形成导电层。处理导电箔以将包含导电层的导电箔的区域与另外的导电箔电隔离。在导电层和阴极迹线之间形成阴极导电对，并且在导电箔和阳极迹线之间形成阳极导电耦合。

3. 发明授权

US08470680B2 Substrate with embedded patterned capacitance 有权
公开(公告)号：US08470680B2
公开(公告)日：2013-06-25
申请号：US12180768
申请日：2008-07-28
申请人： John D. Prymak , Chris Stolarski , Alethia Melody , Antony P. Chacko , Gregory J. Dunn
发明人： John D. Prymak , Chris Stolarski , Alethia Melody , Antony P. Chacko , Gregory J. Dunn
IPC分类号： H01G4/005
CPC分类号： H05K1/162 , H01G9/012 , H01G9/042 , H01G9/045 , H01G9/15 , H05K3/429 , H05K2201/0329 , H05K2201/0355 , H05K2201/09509 , H05K2201/09763 , H05K2201/09909 , H05K2203/0315 , Y10T29/417 , Y10T29/435
摘要： A process for forming a laminate with capacitance and the laminate formed thereby. The process includes the steps of providing a substrate and laminating a conductive foil on the substrate wherein the foil has a dielectric. A conductive layer is formed on the dielectric. The conductive foil is treated to electrically isolate a region of conductive foil containing the conductive layer from additional conductive foil. A cathodic conductive couple is made between the conductive layer and a cathode trace and an anodic conductive couple is made between the conductive foil and an anode trace.

4. 发明申请

US20120106032A1 SUBSTRATE WITH EMBEDDED PATTERNED CAPACITANCE 有权
标题翻译：具有嵌入式图形电容的基板
公开(公告)号：US20120106032A1
公开(公告)日：2012-05-03
申请号：US13345227
申请日：2012-01-06
申请人： John D. Prymak , Chris Stolarski , Alethia Melody , Anthony P. Chacko , Gregory J. Dunn
发明人： John D. Prymak , Chris Stolarski , Alethia Melody , Anthony P. Chacko , Gregory J. Dunn
IPC分类号： H01G9/025 , H01G9/04 , H01G9/15 , H01G7/00
CPC分类号： H05K1/162 , H01G9/012 , H01G9/042 , H01G9/045 , H01G9/15 , H05K3/429 , H05K2201/0329 , H05K2201/0355 , H05K2201/09509 , H05K2201/09763 , H05K2201/09909 , H05K2203/0315 , Y10T29/417 , Y10T29/435
摘要： A process for forming a laminate with capacitance and the laminate formed thereby. The process includes the steps of providing a substrate and laminating a conductive foil on the substrate wherein the foil has a dielectric. A conductive layer is formed on the dielectric. The conductive foil is treated to electrically isolate a region of conductive foil containing the conductive layer from additional conductive foil. A cathodic conductive couple is made between the conductive layer and a cathode trace and an anodic conductive couple is made between the conductive foil and an anode trace.
摘要翻译：一种用于形成具有电容的叠层的方法和由此形成的层压体。该方法包括以下步骤：提供衬底并将导电箔层压在衬底上，其中箔具有电介质。在电介质上形成导电层。处理导电箔以将包含导电层的导电箔的区域与另外的导电箔电隔离。在导电层和阴极迹线之间形成阴极导电对，并且在导电箔和阳极迹线之间形成阳极导电耦合。

5. 发明授权

US08111524B2 Electronic passive device 有权
标题翻译：电子无源器件
公开(公告)号：US08111524B2
公开(公告)日：2012-02-07
申请号：US12526426
申请日：2008-02-12
申请人： Michael S. Randall , Garry Renner , John D. Prymak , Azizuddin Tajuddin
发明人： Michael S. Randall , Garry Renner , John D. Prymak , Azizuddin Tajuddin
IPC分类号： H05K3/00
CPC分类号： H05K1/0231 , H01L23/49827 , H01L23/50 , H01L2224/16225 , H01L2924/3011 , H05K1/141 , H05K2201/10378 , H05K2201/10704 , H05K2201/10734
摘要： A capacitive interposer, electronic package having the capacitive interposer and electronic device with the electronic package is described. The interposer has a first planar face and a second planar face. An array of upper connections is on the first planar face and opposing lower connections are on the second planar face with conduction paths between each upper connection of the upper connections and a lower connection of the lower connections. At least one power feed-through capacitor is provided. The capacitor has a plurality of parallel plates with a dielectric there between. At least one first external termination is in electrical contact with a first set of alternate parallel plates and at least one second external termination is in electrical contact with a second set of alternate parallel plates. The capacitor is mounted on the first planar face with the first external termination in direct electrical contact with a first upper connection and the second external termination is in direct electrical contact with a second upper connection. At least one upper connection, first external termination and second external termination are arranged for direct electrical contact with element contact pads of a common element.
摘要翻译：描述了一种电容式插入器，具有电容插入器的电子封装和具有电子封装的电子器件。插入器具有第一平面和第二平面。上连接的阵列位于第一平面上，相对的下连接在第二平面上，上连接的每个上连接与下连接的下连接之间具有传导路径。提供至少一个馈电电容器。电容器具有多个平行板，其间具有电介质。至少一个第一外部端接件与第一组交替的平行板电接触，并且至少一个第二外部端接件与第二组交替的平行板电接触。电容器安装在第一平面上，第一外部端子与第一上连接件直接电接触，第二外部端子与第二上连接件直接电接触。至少一个上部连接，第一外部端接和第二外部端接布置成与公共元件的元件接触垫直接电接触。

6. 发明授权

US07969711B2 Multiple electronic components: combination capacitor and Zener diode 失效
标题翻译：多电子元件：组合电容和齐纳二极管
公开(公告)号：US07969711B2
公开(公告)日：2011-06-28
申请号：US12026605
申请日：2008-02-06
申请人： John D. Prymak , Eric Jayson Young
发明人： John D. Prymak , Eric Jayson Young
IPC分类号： H01G2/12 , H01G9/00 , H01G9/04 , H01G4/228
CPC分类号： H01G9/0003 , H01G9/012 , H01G9/15 , Y10T29/417 , Y10T29/49169
摘要： A Zener diode—capacitor combination wherein a Zener diode is mounted in the capacitor body and connected in parallel with the capacitor after the capacitor has been voltage tested. A welded strap or jumper wire completing the diode circuit or a connection of separate terminations during soldering may be used to complete the circuit.
摘要翻译：齐纳二极管 - 电容器组合，其中齐纳二极管安装在电容器主体中并且在电容器经过电压测试之后与电容器并联连接。完成二极管电路的焊接带或跳线或焊接期间单独端接的连接可用于完成电路。

7. 发明授权

US07833293B2 Multiple electronic components: combination capacitor and Zener diode 失效
标题翻译：多电子元件：组合电容和齐纳二极管
公开(公告)号：US07833293B2
公开(公告)日：2010-11-16
申请号：US12721104
申请日：2010-03-10
申请人： John D. Prymak , Eric Jayson Young
发明人： John D. Prymak , Eric Jayson Young
IPC分类号： H01G9/00
CPC分类号： H01G9/0003 , H01G9/012 , H01G9/15 , Y10T29/417 , Y10T29/49169
摘要： A Zener diode-capacitor combination wherein a Zener diode is mounted in the capacitor body and connected in parallel with the capacitor after the capacitor has been voltage tested. A welded strap or jumper wire completing the diode circuit or a connection of separate terminations during soldering may be used to complete the circuit.
摘要翻译：齐纳二极管 - 电容器组合，其中齐纳二极管安装在电容器主体中并且在电容器经过电压测试之后与电容器并联连接。完成二极管电路的焊接带或跳线或焊接期间单独端接的连接可用于完成电路。

8. 发明授权

US07164573B1 High ESR or fused ceramic chip capacitor 有权
标题翻译：高ESR或熔融陶瓷片式电容器
公开(公告)号：US07164573B1
公开(公告)日：2007-01-16
申请号：US11216259
申请日：2005-08-31
申请人： John D. Prymak
发明人： John D. Prymak
IPC分类号： H01G4/06
CPC分类号： H01G2/16 , H01G4/232 , H01G4/30
摘要： A fused or high ESR ceramic capacitor for power applications has a fuse or resistor inserted between an end termination and a terminal for one set of alternating conductive plates in the capacitor. The length and thickness of the fuse allows adjustment of the current capability of the fail-open device which provides protection for the circuit in the event of short-circuiting, or the pattern created by the thick-film resistor application defining the added ESR for the capacitor.
摘要翻译：用于电力应用的熔断或高ESR陶瓷电容器在电容器中的一组交替导电板之间具有插入在端部端子和端子之间的保险丝或电阻器。保险丝的长度和厚度允许调整故障开路装置的电流能力，这在短路的情况下为电路提供保护，或者由厚膜电阻器应用产生的图案定义添加的ESR 电容器。

9. 发明授权

US07068490B2 Thermal dissipating capacitor and electrical component comprising same 失效
标题翻译：散热电容器和包含它的电气部件
公开(公告)号：US07068490B2
公开(公告)日：2006-06-27
申请号：US10826605
申请日：2004-04-16
申请人： John D. Prymak
发明人： John D. Prymak
IPC分类号： H01G4/228 , H01G4/20 , H01G4/005
CPC分类号： H01G4/232 , H01G2/065 , H01L23/50 , H01L2924/0002 , H05K1/0203 , H05K1/0231 , H05K2201/10545 , H01L2924/00
摘要： An electrical component with a printed circuit board. The printed circuit board has an upper face and a lower face. A microprocessor is mounted to the upper face. A capacitor is mounted to the lower face. The capacitor has a first face parallel to the printed circuit board and a second face opposite to the first face. First plates and second plates are in alternating planar relationship with a dielectric therebetween and arranged in a plane perpendicular to the plane created by the circuit board. Each first plate has a first coupling tab and a power tab on opposing edges wherein the first coupling tab terminates at the first face and the power tab terminates at the second face. Each second plate of the second plates comprises a second coupling tab and a ground tab on opposing edges wherein the second coupling tab terminates at the first face and the ground tab terminates at the second face. The first coupling tab and the second coupling tab are in electrical contact with the microprocessor.
摘要翻译：具有印刷电路板的电气部件。印刷电路板具有上表面和下表面。微处理器安装在上面。电容器安装在下表面。电容器具有平行于印刷电路板的第一面和与第一面相对的第二面。第一板和第二板与它们之间的电介质处于交替的平面关系，并且布置在与由电路板产生的平面垂直的平面中。每个第一板具有在相对边缘上的第一联接接头和电源接头，其中第一连接接头在第一面处终止，并且电源接头在第二面处终止。第二板的每个第二板包括在相对边缘上的第二联接片和接地片，其中第二连接片在第一面终止并且接地片终止于第二面。第一耦合片和第二耦合片与微处理器电接触。

10. 发明授权

US08760848B2 Concentrated capacitor assembly 有权
标题翻译：集中电容器组件
公开(公告)号：US08760848B2
公开(公告)日：2014-06-24
申请号：US13315931
申请日：2011-12-09
申请人： John D. Prymak , Peter Par Blais , George Haddox , Michael Prevallet , Jim Piller , Chris Stolarski , Chris Wayne
发明人： John D. Prymak , Peter Par Blais , George Haddox , Michael Prevallet , Jim Piller , Chris Stolarski , Chris Wayne
IPC分类号： H01G4/38
CPC分类号： H01G4/38 , H01G4/228
摘要： A capacitor assembly with a substrate having a first face and a second face. A multiplicity of capacitors are mounted on the first face wherein each capacitor has a first lead and a second lead of opposite polarity to the first lead. A bridge is in electrical contact with multiple first leads. A tree is in electrical contact with the bridge wherein the tree passes through a via of the substrate and is in electrical contact with a first trace of the second face. A second trace is on the second face wherein the second lead is in electrical contact with the second trace.
摘要翻译：一种电容器组件，其具有带有第一面和第二面的基板。多个电容器安装在第一面上，其中每个电容器具有与第一引线相反极性的第一引线和第二引线。桥与多个第一引线电接触。树与桥接电接触，其中树通过基底的通孔并与第二面的第一迹线电接触。第二迹线在第二面上，其中第二引线与第二迹线电接触。

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