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1. 发明授权

US4975928A Device for deriving a clock signal using a gated phase-locked loop having means for suspending the gating at device turn-on 失效
标题翻译：用于使用门控锁相环导出时钟信号的装置，具有用于在装置开启时暂停门控的装置
公开(公告)号：US4975928A
公开(公告)日：1990-12-04
申请号：US362531
申请日：1989-06-07
申请人： Johannes B. Horsten
发明人： Johannes B. Horsten
IPC分类号： H04N5/06 , H03L7/08 , H04N5/91 , H04N5/93 , H04N5/932 , H04N7/083
CPC分类号： H04N7/083 , H04N5/932
摘要： A device for deriving a clock signal from an electric signal made up of consecutive signal blocks (B.sub.i), each signal block having a first block section (EBD.sub.i) containing a first signal and a second block section (TBD.sub.i) containing a second signal. The input terminal (1) is coupled to two parallel circuits via a switch (3), one of the parallel circuits including a high-pass filter (8). The circuits have their outputs coupled to the inputs of a phase-locked loop (5) and a code-word detector (6). The output (13) of the code-word detector (6) is coupled to a control signal generator (15). The control signal generator (15) generates control signals which are applied to a control signal input (9) of the switch. During normal operation, the switch (3) defines a time window for the electric signal, so that only the first block sections are applied to the code-word detector (6) and the phase-locked loop (5) to derive the clock signal from the signal information in these first block sections. When the device is switched on, the time window function is disabled. The complete signal is applied to the inputs of the phase-locked loop (5) and the code-word detector (6) via the high-pass filter (8). When the code-word detector (6) has detected a code-word, the timing of the device is in step and changing over to normal gated operation is possible.

2. 发明授权

US4864573A Apparatus for reproducing a pcm modulated signal, comprising a muting circuit 失效
标题翻译：用于再现pcm调制信号的装置，包括静音电路
公开(公告)号：US4864573A
公开(公告)日：1989-09-05
申请号：US93452
申请日：1987-09-04
申请人： Johannes B. Horsten
发明人： Johannes B. Horsten
IPC分类号： G11B20/18
CPC分类号： G11B20/1806 , G11B20/1876
摘要： An apparatus for reproducing a pulse-code-modulated signal comprises error-correction means (3) for correcting errors in one or more of the data words forming the pcm signal. When the error-correction means are no longer capable of correcting errors in the pcm signal, they produce error flags on an output (7), which error flags are applied to a control unit (9). From these error flags the control unit (9) derives a control signal which is applied to a muting unit (6) for switching on the muting unit.A method is described by means of which the control unit derives the control signal from the error flags applied to its input (8). A first auxiliary signal (S.sub.1) is generated if (at least) n.sub.1 error flags are detected within a first time interval (T.sub.1). Subsequently, an i-th auxiliary signal (S.sub.1) is generated if (at least) n.sub.i error flags are detected within an i-th time interval (T.sub.i) which occurs after the instant at which the (i-1)-th auxiliary signal appears. The value of i ranges from 2 to N inclusive. Subsequently, a control-signal generator generates the control signal during a time interval T.sub.m which occurs after the instant at which the N-th auxiliary signal is received (FIG. 2). A number of examples of the control unit are described (FIG. 4).

3. 发明授权

US4853801A Device for regenerating a binary digital signal, for example a bi-phase encoded signal 失效
标题翻译：用于再生二进制数字信号的装置，例如双相编码信号
公开(公告)号：US4853801A
公开(公告)日：1989-08-01
申请号：US61232
申请日：1987-06-10
申请人： Johannes B. Horsten
发明人： Johannes B. Horsten
IPC分类号： G11B20/10 , G11B20/14
CPC分类号： G11B20/1419 , G11B20/10009
摘要： The device comprises an input terminal (1) for receiving an electric signal and an output terminal (2) for supplying the binary digital signal. The input terminal (1) is coupled to the output terminal (2) via an equalizing unit (3) and a limiter circuit (7). The output (5) of the equalizing unit (3) is coupled to a first point of constant potential (16) via a clipper circuit (20). The output (8) of the limiter circuit (7) is coupled to the input (6) via an impedance (23). Further, the input (6) is coupled to a second point of constant potential (earth) via an integrating element (24). FIG. 1.

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