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1. 发明授权

US5744980A Flexible, high-performance static RAM architecture for field-programmable gate arrays 失效
标题翻译：用于现场可编程门阵列的灵活高性能静态RAM架构
公开(公告)号：US5744980A
公开(公告)日：1998-04-28
申请号：US603597
申请日：1996-02-16
申请人： John E. McGowan , William C. Plants , Joel D. Landry , Sinan Kaptanoglu , Warren K. Miller
发明人： John E. McGowan , William C. Plants , Joel D. Landry , Sinan Kaptanoglu , Warren K. Miller
IPC分类号： H03K19/177
CPC分类号： H03K19/1776 , H03K19/17704
摘要： A field programmable gate array architecture comprises a plurality of horizontal and vertical routing channels each including a plurality of interconnect conductors. Some interconnect conductors are segmented by user-programmable interconnect elements, and some horizontal and vertical interconnect conductors are connectable by user-programmable interconnect elements located at selected intersections between them. An array of rows and columns of logic function modules each having at least one input and one output is superimposed on the routing channels. The inputs and outputs of the logic function modules are connectable to ones of the interconnect conductors in either or both of the horizontal and vertical routing channels. At least one column of random access memory blocks is disposed in the array. Each random access memory block spans a distance of more than one row of the array such that more than one horizontal routing channel passes therethrough and is connectable to adjacent logic function modules on either side thereof. Each of the random access memory blocks has address inputs, control inputs, data inputs, and data outputs. User-programmable interconnect elements are connected between the address inputs, control inputs, data inputs, and data outputs of the random access memory blocks and selected ones of the interconnect conductors in the horizontal routing channels passing therethrough. Programming circuitry is provided for programming selected ones of the user-programmable interconnect conductors to connect the inputs and outputs of the logic function modules to one another and to the address inputs, control inputs, data inputs, and data outputs of the random access memory blocks.
摘要翻译：现场可编程门阵列架构包括多个水平和垂直路由通道，每个路由通道包括多个互连导体。一些互连导体由用户可编程互连元件分段，并且一些水平和垂直互连导体可由位于它们之间的选定交叉处的用户可编程互连元件连接。每个具有至少一个输入和一个输出的逻辑功能模块的行和列阵列叠加在路由信道上。逻辑功能模块的输入和输出可连接到水平和垂直路由通道中的一个或两者中的互连导体中的一个。至少一列随机存取存储器块被布置在阵列中。每个随机存取存储器块跨越阵列的多于一行的距离，使得多于一个的水平路由信道通过其中并且可连接到其任一侧的相邻逻辑功能模块。每个随机存取存储块具有地址输入，控制输入，数据输入和数据输出。用户可编程互连元件连接在随机存取存储器块的地址输入，控制输入，数据输入和数据输出以及通过其中的水平路由通道中的选定的互连导体。提供了编程电路，用于编程用户可编程互连导体中的所选择的一个以将逻辑功能模块的输入和输出彼此连接，并将随机存取存储器块的地址输入，控制输入，数据输入和数据输出。

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