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1. 发明授权

US08836442B2 Variable capacitance with delay lock loop 有权
标题翻译：具有延迟锁定环路的可变电容
公开(公告)号：US08836442B2
公开(公告)日：2014-09-16
申请号：US13008748
申请日：2011-01-18
申请人： Jody Greenberg , Sehat Sutardja
发明人： Jody Greenberg , Sehat Sutardja
IPC分类号： H03B5/04 , H03B5/12 , H03K7/08 , H03B5/02 , H03L7/22 , H03L1/02 , H03L7/07 , H03L7/08 , H03L7/081 , H03L7/099
CPC分类号： H03B5/02 , H03B5/04 , H03B5/1215 , H03B5/1228 , H03B5/1265 , H03B2200/005 , H03B2201/0266 , H03J2200/10 , H03K7/08 , H03L1/022 , H03L1/026 , H03L7/07 , H03L7/08 , H03L7/0812 , H03L7/099 , H03L7/22
摘要： An integrated circuit includes a delay lock loop (DLL) circuit that generates incremental delay line signals and a delay line output signal based on a received clock signal. A pulse-width modulation (PWM) control module generates a PWM control signal. A variable capacitance circuit is controlled based on the delay line output signal, the PWM control signal, and one of the incremental delay line signals.
摘要翻译：集成电路包括延迟锁定环（DLL）电路，其基于接收的时钟信号产生增量延迟线信号和延迟线输出信号。脉冲宽度调制（PWM）控制模块产生PWM控制信号。可变电容电路根据延迟线输出信号，PWM控制信号和增量延迟线信号之一进行控制。

2. 发明申请

US20070024292A1 On-die heating circuit and control loop for rapid heating of the die 有权
标题翻译：片上加热电路和控制回路，用于模具的快速加热
公开(公告)号：US20070024292A1
公开(公告)日：2007-02-01
申请号：US11243017
申请日：2005-10-03
申请人： Jody Greenberg , Sehat Sutardja
发明人： Jody Greenberg , Sehat Sutardja
IPC分类号： G01R27/08
CPC分类号： G01R31/2875 , G01R31/2856
摘要： An integrated circuit includes a heating circuit configured to heat the integrated circuit under the control of a controller. A transfer function with adjustable pole, zero and overall gain is implemented in the controller such that a temperature response of the integrated circuit can be changed by adjusting one or more of the adjustable pole, zero and overall gain.
摘要翻译：集成电路包括被配置为在控制器的控制下加热集成电路的加热电路。在控制器中实现具有可调极点，零和总增益的传递函数，使得集成电路的温度响应可以通过调节可调极点，零和总体增益中的一个或多个来改变。

3. 发明授权

US08044701B1 Digitally tunable capacitor 有权
标题翻译：数字可调谐电容
公开(公告)号：US08044701B1
公开(公告)日：2011-10-25
申请号：US12905657
申请日：2010-10-15
申请人： Jody Greenberg
发明人： Jody Greenberg
IPC分类号： H03K5/00
CPC分类号： H03J1/00 , H03B5/1215 , H03B5/1228 , H03B5/1265 , H03J2200/10
摘要： The disclosed device can contain a pair of switchable capacitors, one of which has the larger capacitance of the pair. Each of the switchable capacitors can include a capacitor in series with a switch. Both switchable capacitors can be connected in a parallel circuit that has a tunable capacitance. The ratio of the capacitances of the pair can approximately equal a ratio of mutually prime integers. In a particular case, the ratio of capacitances can approximately equal a ratio of two consecutive integers. The capacitance ratio can be called a weight or weight ratio. A switch controller can drive the pair of switchable capacitors with a pair of (M+1)-ary pulse width modulated signals, each of which has the same modulation period.
摘要翻译：所公开的装置可以包含一对可切换电容器，其中一个电容器具有较大的电容。每个可开关电容器可以包括与开关串联的电容器。两个可切换电容器可以连接在具有可调谐电容的并联电路中。该对的电容的比率可以近似等于互相整数的比率。在特定情况下，电容的比率可以近似等于两个连续整数的比率。电容比可以称为重量或重量比。开关控制器可以用一对（M + 1）个脉冲宽度调制信号驱动该对可切换电容器，每一个具有相同的调制周期。

4. 发明授权

US07872542B2 Variable capacitance with delay lock loop 有权
标题翻译：具有延迟锁定环路的可变电容
公开(公告)号：US07872542B2
公开(公告)日：2011-01-18
申请号：US12180853
申请日：2008-07-28
申请人： Jody Greenberg , Sehat Sutardja
发明人： Jody Greenberg , Sehat Sutardja
IPC分类号： H03B1/00 , H03K7/08
CPC分类号： H03B5/02 , H03B5/04 , H03B5/1215 , H03B5/1228 , H03B5/1265 , H03B2200/005 , H03B2201/0266 , H03J2200/10 , H03K7/08 , H03L1/022 , H03L1/026 , H03L7/07 , H03L7/08 , H03L7/0812 , H03L7/099 , H03L7/22
摘要： An integrated circuit includes a delay lock loop (DLL) circuit that generates incremental delay line signals and a delay line output signal based on a received clock signal. A pulse-width modulation (PWM) control module generates a PWM control signal. A tunable circuit having variable capacitance is controlled based on the delay line output signal, the PWM control signal, and one of the incremental delay line signals.
摘要翻译：集成电路包括延迟锁定环（DLL）电路，其基于接收的时钟信号产生增量延迟线信号和延迟线输出信号。脉冲宽度调制（PWM）控制模块产生PWM控制信号。基于延迟线输出信号，PWM控制信号和增量延迟线信号之一来控制具有可变电容的可调谐电路。

5. 发明申请

US20080122549A1 LOW-NOISE HIGH-STABILITY CRYSTAL OSCILLATOR 有权
标题翻译：低噪声高稳定性晶体振荡器
公开(公告)号：US20080122549A1
公开(公告)日：2008-05-29
申请号：US11935271
申请日：2007-11-05
申请人： Jody Greenberg
发明人： Jody Greenberg
IPC分类号： H03L5/00
CPC分类号： H03L5/00 , H03B5/364
摘要： Circuits, methods, and apparatus that provide low-noise, high-stability crystal oscillators having controlled-amplitude differential output signals and DC level control. A crystal oscillator circuit has two feedback loops, one for setting the DC level of its signals, the other for adjusting the amplitude of those signals. The DC level feedback loop can set the DC component of the oscillator signals to a voltage midway between two supply voltages. The amplitude control loop sets the amplitude of the output of the crystal oscillator signal to be within a range. The amplitude can be set to provide a maximum swing without clipping the supply voltages in order to provide high-stability and minimal jitter. The amplitude control circuit can also be digital for improved noise performance. The time constants of these two loops can be separated such that instabilities are avoided.
摘要翻译：提供具有受控幅度差分输出信号和DC电平控制的低噪声，高稳定性晶体振荡器的电路，方法和装置。晶体振荡器电路具有两个反馈回路，一个用于设置其信号的直流电平，另一个用于调整这些信号的幅度。 DC电平反馈环路可以将振荡器信号的直流分量设置为两个电源电压之间的一个电压。振幅控制回路将晶体振荡器信号的输出振幅设定在一个范围内。可以设置幅度以提供最大摆幅而不削减电源电压，以便提供高稳定性和最小的抖动。幅度控制电路也可以是数字的，以提高噪声性能。这两个循环的时间常数可以分开，以避免不稳定。

6. 发明授权

US07375597B2 Low-noise fine-frequency tuning 有权
标题翻译：低噪声微调频率
公开(公告)号：US07375597B2
公开(公告)日：2008-05-20
申请号：US11242230
申请日：2005-10-03
申请人： Jody Greenberg , Sehat Sutardja
发明人： Jody Greenberg , Sehat Sutardja
IPC分类号： H03B1/00
CPC分类号： H03L1/022 , H03B5/02 , H03B5/1212 , H03B5/1228 , H03B5/1265 , H03B2200/0088 , H03L1/026
摘要： Circuits, methods, apparatus, and code that provide low-noise and high-resolution electronic circuit tuning. An exemplary embodiment of the present invention adjusts a capacitance value by pulse-width modulating a control voltage for a switch in series with a capacitor. The pulse-width-modulated control signal can be adjusted using entry values found in a lookup table, by using analog or digital control signals, or by using other appropriate methods. The capacitance value tunes a frequency response or characteristic of an electronic circuit. The response can be made to be insensitive to conditions such as temperature, power supply voltage, or processing.
摘要翻译：提供低噪声和高分辨率电子电路调谐的电路，方法，设备和代码。本发明的示例性实施例通过对与电容器串联的开关的控制电压进行脉宽调制来调整电容值。脉冲宽度调制控制信号可以通过使用模拟或数字控制信号或使用其他适当方法在查找表中找到的条目值进行调整。电容值调节电子电路的频率响应或特性。可以对温度，电源电压或处理等条件不敏感。

7. 发明授权

US07292114B2 Low-noise high-stability crystal oscillator 有权
标题翻译：低噪声高稳定晶体振荡器
公开(公告)号：US07292114B2
公开(公告)日：2007-11-06
申请号：US11242621
申请日：2005-10-03
申请人： Jody Greenberg
发明人： Jody Greenberg
IPC分类号： H03B5/32
CPC分类号： H03L5/00 , H03B5/364
摘要： Circuits, methods, and apparatus that provide low-noise, high-stability crystal oscillators having controlled-amplitude differential output signals and DC level control. A crystal oscillator circuit has two feedback loops, one for setting the DC level of its signals, the other for adjusting the amplitude of those signals. The DC level feedback loop can set the DC component of the oscillator signals to a voltage midway between two supply voltages. The amplitude control loop sets the amplitude of the output of the crystal oscillator signal to be within a range. The amplitude can be set to provide a maximum swing without clipping the supply voltages in order to provide high-stability and minimal jitter. The amplitude control circuit can also be digital for improved noise performance. The time constants of these two loops can be separated such that instabilities are avoided.
摘要翻译：提供具有受控幅度差分输出信号和DC电平控制的低噪声，高稳定性晶体振荡器的电路，方法和装置。晶体振荡器电路具有两个反馈回路，一个用于设置其信号的直流电平，另一个用于调整这些信号的幅度。 DC电平反馈环路可以将振荡器信号的直流分量设置为两个电源电压之间的一个电压。振幅控制回路将晶体振荡器信号的输出振幅设定在一个范围内。可以设置幅度以提供最大摆幅而不削减电源电压，以便提供高稳定性和最小的抖动。幅度控制电路也可以是数字的，以提高噪声性能。这两个循环的时间常数可以分开，以避免不稳定。

8. 发明申请

US20070211819A1 All digital implementation of clock spectrum spreading (dither) for low power/die area 有权
公开(公告)号：US20070211819A1
公开(公告)日：2007-09-13
申请号：US11803100
申请日：2007-05-11
申请人： Jody Greenberg
发明人： Jody Greenberg
IPC分类号： H04L27/00
CPC分类号： H04B15/04 , H03K3/84 , H03K7/06 , H03L7/06 , H04B2215/064 , H04B2215/067
摘要： A digital circuit configured to spread a clock train spectrum includes a clock configured to generate the clock train, and a variable divider configured to divide the frequency of the clock train by a temporally-varying-divider value to modulate the clock train and generate a dithered clock train. The circuit further includes a first accumulator configured to accumulate the dithered clock train to generate a frequency modulation waveform, and a second accumulator configured accumulate the frequency modulated waveform to generate a phase modulation signal. The circuit further includes a phase-value calculator configured to calculate the temporally-varying divider value based on the phase modulation signal; and a closed-loop control circuit configured to track and filter the modulation of the dithered clock train to generate a second clock train that is the spread spectrum of the first mentioned clock train.

9. 发明申请

US20070024385A1 Low-noise high-stability crystal oscillator 有权
公开(公告)号：US20070024385A1
公开(公告)日：2007-02-01
申请号：US11242621
申请日：2005-10-03
申请人： Jody Greenberg
发明人： Jody Greenberg
IPC分类号： H03B5/32
CPC分类号： H03L5/00 , H03B5/364
摘要： Circuits, methods, and apparatus that provide low-noise, high-stability crystal oscillators having controlled-amplitude differential output signals and DC level control. A crystal oscillator circuit has two feedback loops, one for setting the DC level of its signals, the other for adjusting the amplitude of those signals. The DC level feedback loop can set the DC component of the oscillator signals to a voltage midway between two supply voltages. The amplitude control loop sets the amplitude of the output of the crystal oscillator signal to be within a range. The amplitude can be set to provide a maximum swing without clipping the supply voltages in order to provide high-stability and minimal jitter. The amplitude control circuit can also be digital for improved noise performance. The time constants of these two loops can be separated such that instabilities are avoided.

10. 发明授权

US08717114B2 Low-noise fine-frequency tuning 失效
标题翻译：低噪声微调频率
公开(公告)号：US08717114B2
公开(公告)日：2014-05-06
申请号：US13022983
申请日：2011-02-08
申请人： Jody Greenberg , Sehat Sutardja
发明人： Jody Greenberg , Sehat Sutardja
IPC分类号： H03L1/02
CPC分类号： H03L1/022 , H03B5/02 , H03B5/1212 , H03B5/1228 , H03B5/1265 , H03B2200/0088 , H03L1/026
摘要： Circuits, methods, apparatus, and code that provide low-noise and high-resolution electronic circuit tuning. An exemplary embodiment of the present invention adjusts a capacitance value by pulse-width modulating a control voltage for a switch in series with a capacitor. The pulse-width-modulated control signal can be adjusted using entry values found in a lookup table, by using analog or digital control signals, or by using other appropriate methods. The capacitance value tunes a frequency response or characteristic of an electronic circuit. The response can be made to be insensitive to conditions such as temperature, power supply voltage, or processing.
摘要翻译：提供低噪声和高分辨率电子电路调谐的电路，方法，设备和代码。本发明的示例性实施例通过对与电容器串联的开关的控制电压进行脉宽调制来调整电容值。脉冲宽度调制控制信号可以通过使用模拟或数字控制信号或使用其他适当方法在查找表中找到的条目值进行调整。电容值调节电子电路的频率响应或特性。可以对温度，电源电压或处理等条件不敏感。

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