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1. 发明授权

US08470685B2 Integration of self-aligned trenches in-between metal lines 有权
标题翻译：在金属线之间集成自对准沟槽
公开(公告)号：US08470685B2
公开(公告)日：2013-06-25
申请号：US12161456
申请日：2007-01-11
申请人： Joaquin Torres , Laurent-Georges Gosset
发明人： Joaquin Torres , Laurent-Georges Gosset
IPC分类号： H01L21/76
CPC分类号： H01L21/7682 , H01L21/76885 , H01L23/5222 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides an improved method of forming air cavities to overcome IC via-misalignment issues. The method of forming air cavity trenches in-between metal lines of an integrated circuit includes the steps of partially removing (42) an intertrack dielectric deposited on an interconnect structure surface to control the height between the top surface of a metal line of the interconnect surface and the surface of the intertrack dielectric; depositing (44) a dielectric liner on the interconnect surface; removing (46) at least part of the dielectric liner on the interconnect surface; successively repeating (48) the deposition of the dielectric liner and the removal of the dielectric liner on the interconnect surface in so far as the interconnect surface is sufficiently protected by a remaining dielectric liner for forming of the plurality of air cavity trenches; and forming (50) at least one air cavity trench in-between the metal lines by etching the intertrack dielectric material.
摘要翻译：本发明提供了一种形成空气腔以改善IC通过失准问题的改进方法。在集成电路的金属线之间形成空气腔沟槽的方法包括以下步骤：部分地去除（42）沉积在互连结构表面上的介质电介质，以控制互连表面的金属线的顶表面之间的高度和交织电介质的表面; 在所述互连表面上沉积（44）电介质衬垫; 在所述互连表面上移除（46）所述电介质衬垫的至少一部分; 在互连表面被用于形成多个空气腔沟槽的剩余电介质衬垫充分保护的范围内连续重复（48）电介质衬垫的沉积和电介质衬垫在互连表面上的移除; 以及通过蚀刻所述轨道间介电材料，在所述金属线之间形成（50）至少一个气腔沟槽。

2. 发明授权

US08138082B2 Method for forming metal interconnects in a dielectric material 有权
标题翻译：在电介质材料中形成金属互连的方法
公开(公告)号：US08138082B2
公开(公告)日：2012-03-20
申请号：US12280978
申请日：2007-02-26
申请人： Joaquin Torres , Vincent Arnal , Laurent-Georges Gosset , Wim Besling
发明人： Joaquin Torres , Vincent Arnal , Laurent-Georges Gosset , Wim Besling
IPC分类号： H01L21/4763
CPC分类号： H01L21/76835 , H01L21/76807 , H01L21/76814 , H01L21/76831 , H01L21/76844
摘要： A semiconductor device includes an interconnect having electrically conductive portions and a dielectric layer made of a first dielectric material. A trench is formed in the dielectric layer. The exposed portions of the dielectric layer which form the side walls of the trench are removed. A dielectric liner is then deposited on the side walls of the trench, the liner being made of a second dielectric material.
摘要翻译：半导体器件包括具有导电部分和由第一介电材料制成的电介质层的互连。在电介质层中形成沟槽。去除形成沟槽侧壁的电介质层的露出部分。然后将电介质衬垫沉积在沟槽的侧壁上，衬垫由第二电介质材料制成。

3. 发明申请

US20110080686A1 MIM CAPACITOR 有权
标题翻译： MIM电容器
公开(公告)号：US20110080686A1
公开(公告)日：2011-04-07
申请号：US12775103
申请日：2010-05-06
申请人： Alexis Farcy , Maryline Thomas , Joaquin Torres , Sonarith Chhun , Laurent-Georges Gosset
发明人： Alexis Farcy , Maryline Thomas , Joaquin Torres , Sonarith Chhun , Laurent-Georges Gosset
IPC分类号： H01G7/00
CPC分类号： H01G4/005 , H01G4/008 , Y10T29/43 , Y10T29/435 , Y10T29/49002
摘要： A method of forming a metal-insulator-metal capacitor having top and bottom plates separated by a dielectric layer, one of the top and bottom plates having at least one protrusion extending into a corresponding cavity in the other of the top and bottom plates, the method including the steps of growing one or more nanofibers on a base surface.
摘要翻译：一种形成金属 - 绝缘体 - 金属电容器的方法，其具有由电介质层隔开的顶板和底板，所述顶板和底板中的一个具有延伸到顶板和底板中的另一个中的相应空腔中的至少一个突起，方法包括在基底表面上生长一个或多个纳米纤维的步骤。

4. 发明申请

US20110006430A1 COPPER DIFFUSION BARRIER 有权
标题翻译：铜扩散障碍物
公开(公告)号：US20110006430A1
公开(公告)日：2011-01-13
申请号：US12882577
申请日：2010-09-15
申请人： Nicolas Jourdan , Joaquin Torres
发明人： Nicolas Jourdan , Joaquin Torres
IPC分类号： H01L23/532
CPC分类号： H01L21/76843 , H01L21/76831 , H01L21/76864 , H01L21/76868 , H01L21/76873 , H01L23/53238 , H01L2221/1089 , H01L2924/0002 , H01L2924/00
摘要： The invention concerns a method of forming a copper portion surrounded by an insulating material in an integrated circuit structure, the insulating material being a first oxide, the method having steps including forming a composite material over a region of the insulating material where the copper portion is to be formed, the composite material having first and second materials, annealing such that the second material reacts with the insulating material to form a second oxide that provides a diffusion barrier to copper; and depositing a copper layer over the composite material by electrochemical deposition to form the copper portion.
摘要翻译：本发明涉及一种形成由集成电路结构中的绝缘材料包围的铜部分的方法，绝缘材料是第一氧化物，该方法包括在绝缘材料的区域上形成复合材料，其中铜部分为要形成的具有第一和第二材料的复合材料退火，使得第二材料与绝缘材料反应以形成向铜提供扩散阻挡层的第二氧化物; 以及通过电化学沉积在复合材料上沉积铜层以形成铜部分。

5. 发明申请

US20100090346A1 INTEGRATION OF SELF-ALIGNED TRENCHES IN-BETWEEN METAL LINES 有权
标题翻译：在金属线之间的自对准铁素体的整合
公开(公告)号：US20100090346A1
公开(公告)日：2010-04-15
申请号：US12161456
申请日：2007-01-11
申请人： Joaquin Torres , Laurent-Georges Gosset
发明人： Joaquin Torres , Laurent-Georges Gosset
IPC分类号： H01L23/48 , H01L21/311
CPC分类号： H01L21/7682 , H01L21/76885 , H01L23/5222 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides an improved method of forming air cavities to overcome IC via-misalignment issues. The method of forming air cavity trenches in-between metal lines of an integrated circuit includes the steps of partially removing (42) an intertrack dielectric deposited on an interconnect structure surface to control the height between the top surface of a metal line of the interconnect surface and the surface of the intertrack dielectric; depositing (44) a dielectric liner on the interconnect surface; removing (46) at least part of the dielectric liner on the interconnect surface; successively repeating (48) the deposition of the dielectric liner and the removal of the dielectric liner on the interconnect surface in so far as the interconnect surface is sufficiently protected by a remaining dielectric liner for forming of the plurality of air cavity trenches; and forming (50) at least one air cavity trench in-between the metal lines by etching the intertrack dielectric material.
摘要翻译：本发明提供了一种形成空气腔以改善IC通过失准问题的改进方法。在集成电路的金属线之间形成空气腔沟槽的方法包括以下步骤：部分地去除（42）沉积在互连结构表面上的介质电介质，以控制互连表面的金属线的顶表面之间的高度和交织电介质的表面; 在所述互连表面上沉积（44）电介质衬垫; 在所述互连表面上移除（46）所述电介质衬垫的至少一部分; 在互连表面被用于形成多个空气腔沟槽的剩余电介质衬垫充分保护的范围内连续重复（48）电介质衬垫的沉积和电介质衬垫在互连表面上的移除; 以及通过蚀刻所述轨道间介电材料，在所述金属线之间形成（50）至少一个气腔沟槽。

6. 发明申请

US20100044865A1 FABRICATION OF A DIFFUSION BARRIER CAP ON COPPER CONTAINING CONDUCTIVE ELEMENTS 有权
标题翻译：包含导电元件的扩散阻挡层的制造
公开(公告)号：US20100044865A1
公开(公告)日：2010-02-25
申请号：US12516127
申请日：2007-11-27
申请人： Joaquin Torres , Laurent Gosset , Vincent Arnal , Sonarith Chhun
发明人： Joaquin Torres , Laurent Gosset , Vincent Arnal , Sonarith Chhun
IPC分类号： H01L21/768 , H01L23/48
CPC分类号： H01L21/76849 , H01L21/7682 , H01L21/76822 , H01L21/76826 , H01L21/76829 , H01L21/76856 , H01L21/76867 , H01L21/76886 , H01L23/53238 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： A method for fabricating a self-aligned diffusion-barrier cap on a Cu-containing conductive element in an integrated-circuit device comprises:—providing a substrate having a Cu-containing conductive element embedded laterally into a dielectric layer and having an exposed surface;—depositing a metal layer on the exposed surface of conductive element;—inducing diffusion of metal from the metal layer into a top section of the conductive element;—removing the remaining metal layer;—letting diffused metal in the top section of the conductive element and particles of a second constituent react with each other so as to build a compound covering the conductive element. The metal of the metal layer and the second constituent are chosen so that the compound forms a diffusion barrier against Cu diffusion. A reduction the dielectric constant of the dielectric material in an interconnect stack of an integrated-circuit device is achieved.
摘要翻译：一种用于在集成电路器件中的含Cu导电元件上制造自对准扩散阻挡帽的方法包括： - 将具有横向嵌入电介质层并具有暴露表面的含Cu导电元件的衬底提供; - 将金属层沉积在导电元件的暴露表面上; - 将金属从金属层扩散到导电元件的顶部; - 移除剩余的金属层; - 在导电元件的顶部中引入扩散金属并且第二组分的颗粒彼此反应，以便构成覆盖导电元件的化合物。选择金属层和第二组分的金属，使得该化合物形成针对Cu扩散的扩散阻挡层。实现了集成电路器件的互连叠层中介电材料的介电常数的降低。

7. 发明申请

US20090272565A1 CONTROL OF CARBON NANOSTRUCTURE GROWTH IN AN INTERCONNECT STRUCTURE 有权
标题翻译：碳互连结构中碳纳米管生长的控制
公开(公告)号：US20090272565A1
公开(公告)日：2009-11-05
申请号：US12439919
申请日：2007-08-29
申请人： Laurent Gosset , Joaquin Torres
发明人： Laurent Gosset , Joaquin Torres
IPC分类号： H05K1/09 , B05D5/12 , H01L21/768
CPC分类号： H01L29/0665 , B82Y10/00 , H01L21/76831 , H01L21/76879 , H01L29/0673 , H01L29/0676 , H01L2221/1094
摘要： An interconnect structure on a substrate is provided. The interconnect structure comprises electrically conductive interconnect elements on at least two interconnect levels on or above a substrate level. In the interconnect structure of the invention, at least one electrically conductive via connects a first interconnect element on one interconnect level or on the substrate level to a second interconnect element on a different interconnect level. The via extends in a via opening of a first dielectric layer and comprises an electrically conductive via material that contains electrically conductive cylindrical carbon nanostructures. At least one cover-layer segment reaches into a lateral extension of the via opening and defines a via aperture that is small enough to prevent a penetration of the carbon nanostructures through the via aperture. This structure enhances control of carbon nanostructure growth in a height direction during fabrication of the interconnect structure.
摘要翻译：提供了衬底上的互连结构。互连结构包括在衬底层上或上方的至少两个互连层上的导电互连元件。在本发明的互连结构中，至少一个导电通孔将一个互连层上的第一互连元件或衬底层上的第一互连元件连接到不同互连层上的第二互连元件。通孔在第一电介质层的通孔中延伸，并且包括含有导电圆柱形碳纳米结构的导电通孔材料。至少一个覆盖层段到达通孔开口的横向延伸部分，并限定通孔孔，其足够小以防止碳纳米结构穿过通孔。该结构在互连结构的制造期间增强了在高度方向上碳纳米结构生长的控制。

8. 发明授权

US07553739B2 Integration control and reliability enhancement of interconnect air cavities 有权
标题翻译：互连空气腔的集成控制和可靠性增强
公开(公告)号：US07553739B2
公开(公告)日：2009-06-30
申请号：US11456657
申请日：2006-07-11
申请人： Joaquin Torres , Laurent-Georges Gosset
发明人： Joaquin Torres , Laurent-Georges Gosset
IPC分类号： H01L21/44 , H01L23/48
CPC分类号： H01L21/76831 , H01L21/7682 , H01L21/76849
摘要： An improved semiconductor device, integrated circuit, and integrated circuit fabrication method introduce highly controlled air cavities within high-speed copper interconnects. A polymer material is introduced on the edges of interconnect lines and vias within an interconnect stack. This incorporates and controls air cavities formation, thus enhancing the signal propagation performance of the semiconductor interconnects.
摘要翻译：改进的半导体器件，集成电路和集成电路制造方法在高速铜互连中引入高度受控制的空气腔。聚合物材料被引入互连线的边缘和互连叠层内的通孔。这包括和控制空气腔形成，从而增强半导体互连的信号传播性能。

9. 发明申请

US20090051033A1 RELIABILITY IMPROVEMENT OF METAL-INTERCONNECT STRUCTURE BY CAPPING SPACERS 审中-公开
标题翻译：金属互连结构的可靠性改进
公开(公告)号：US20090051033A1
公开(公告)日：2009-02-26
申请号：US12159652
申请日：2006-12-19
申请人： Laurent Gosset , Vincent Arnal , Mohamed Aimadeddine , Joaquin Torres
发明人： Laurent Gosset , Vincent Arnal , Mohamed Aimadeddine , Joaquin Torres
IPC分类号： H01L21/768 , H01L23/522
CPC分类号： H01L23/53238 , H01L21/76832 , H01L21/76834 , H01L21/76849 , H01L21/76852 , H01L21/76865 , H01L21/76885 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： The present invention relates to a metal-interconnect structure for electrically connecting integrated-circuit elements in an integrated-circuit device. It solves several problems of operational reliability in damascene interconnect structures, due to corner effects and structural defects present at top edges of interconnect lines fabricated according to prior-art processing technologies. In alternative configurations of the metal interconnect structure, capping spacers (334) are arranged abutting and covering outer top edges (316c) of interconnect lines (304) or lateral barrier liners (316), respectively. The interconnect structure of the invention eliminates the negative influence of these critical regions in the metal-interconnect structure on the operational reliability of an integrated-circuit device.
摘要翻译：本发明涉及用于将集成电路器件中的集成电路元件电连接的金属互连结构。它解决了镶嵌互连结构中的几个操作可靠性问题，这是由于根据现有技术处理技术制造的互连线的顶部边缘处的拐角效应和结构缺陷。在金属互连结构的替代配置中，封盖间隔件（334）被分别邻接和覆盖互连线（304）或侧向阻挡衬里（316）的外顶边缘（316c）。本发明的互连结构消除了金属互连结构中的这些关键区域对集成电路器件的操作可靠性的负面影响。

10. 发明申请

US20080179750A1 INTERCONNECTIONS OF AN INTEGRATED ELECTRONIC CIRCUIT 审中-公开
标题翻译：一体化电子电路的互连
公开(公告)号：US20080179750A1
公开(公告)日：2008-07-31
申请号：US12013279
申请日：2008-01-11
申请人： Vincent Arnal , Joaquin Torres
发明人： Vincent Arnal , Joaquin Torres
IPC分类号： H01L21/768 , H01L23/522
CPC分类号： H01L23/53295 , H01L21/76808 , H01L21/7682 , H01L21/76835 , H01L23/5222 , H01L23/5226 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： An integrated electronic circuit includes superimposed insulating layers and metal elements distributed within said insulating layers. Each insulating layer comprises a first level within which the metal elements lie substantially in the plane of said first level, and a second level traversed by the metal elements in a direction substantially perpendicular to the plane of said second level, so as to come into contact with at least one metal element of the first level. The levels also comprise insulation zones for insulating the metal elements from each other. For at least one insulating layer, at least one of the levels of said at least one insulating layer comprises at least two insulation zones respectively realized of a first material and a second material which are different from each other.
摘要翻译：集成电子电路包括叠加的绝缘层和分布在所述绝缘层内的金属元件。每个绝缘层包括第一级，其中金属元件基本上位于所述第一级的平面内，第二级由金属元件沿基本上垂直于所述第二级的平面的方向穿过，以便接触具有至少一个第一级的金属元件。这些电平还包括用于使金属元件彼此绝缘的绝缘区。对于至少一个绝缘层，所述至少一个绝缘层的至少一个级别包括分别实现彼此不同的第一材料和第二材料的至少两个绝缘区域。

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