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1. 发明申请

US20170345494A1 SEMICONDUCTOR DEVICES INCLUDING AUXILIARY BIT LINES 审中-公开
公开(公告)号：US20170345494A1
公开(公告)日：2017-11-30
申请号：US15681910
申请日：2017-08-21
申请人： Joonhee Lee , Jiyoung Kim , Jintaek Park , Seong Soon Cho
发明人： Joonhee Lee , Jiyoung Kim , Jintaek Park , Seong Soon Cho
IPC分类号： G11C13/00 , H01L27/24
CPC分类号： G11C13/0026 , G11C13/0004 , G11C13/0007 , G11C2213/53 , G11C2213/71 , G11C2213/75 , H01L27/24 , H01L27/2454 , H01L27/2481
摘要： Semiconductor devices are provided. A semiconductor device includes a stack of alternating gates and insulating layers. The semiconductor device includes a dummy cell region. The semiconductor device includes a plurality of bit lines and a plurality of auxiliary bit lines. Some of the plurality of auxiliary bit lines have different respective lengths. Related methods of forming semiconductor devices are also provided.

2. 发明授权

US09165935B2 Semiconductor devices and methods for manufacturing the same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US09165935B2
公开(公告)日：2015-10-20
申请号：US13533373
申请日：2012-06-26
申请人： Hyun-Woo Chung , Jiyoung Kim , Yongchul Oh , Sungkwan Choi , Yoosang Hwang
发明人： Hyun-Woo Chung , Jiyoung Kim , Yongchul Oh , Sungkwan Choi , Yoosang Hwang
IPC分类号： H01L27/108
CPC分类号： H01L27/10876 , H01L27/10823
摘要： A semiconductor device includes a semiconductor substrate including first trenches defining outer sidewalls of a pair of active pillars and a second trench defining opposing inner sidewalls of the pair of active pillars. The second trench may have a bottom surface located at a higher level than bottom surface of the first trench. Auxiliary conductive lines may be disposed in the first trenches to cover and cross the outer sidewalls of the pair of active pillars. A pair of main conductive lines may be disposed in a pair of recessed regions that are laterally recessed from lower portions of the inner sidewalls of the active pillars into the pair of active pillars. A common impurity region may be disposed in the semiconductor substrate under the second trench. Upper impurity regions may be disposed in upper portions of the active pillars.
摘要翻译：半导体器件包括半导体衬底，其包括限定一对有源柱的外侧壁的第一沟槽和限定该对有源柱的相对内侧壁的第二沟槽。第二沟槽可以具有位于比第一沟槽的底表面更高的水平面的底表面。辅助导线可以设置在第一沟槽中以覆盖并穿过该对活动柱的外侧壁。一对主导线可以设置在从活动柱的内侧壁的下部侧向凹入一对活动柱的一对凹陷区域中。可以在第二沟槽下方的半导体衬底中设置公共杂质区域。上部杂质区域可以设置在活性支柱的上部。

3. 外观设计

USD659000S1 Bottle 有权
公开(公告)号：USD659000S1
公开(公告)日：2012-05-08
申请号：US29360697
申请日：2010-04-29
申请人： Grace Jiyoung Kim , J. Steven Little , James J. Miller
设计人： Grace Jiyoung Kim , J. Steven Little , James J. Miller

4. 发明授权

US08987111B2 Method of manufacturing a three dimensional array having buried word lines of different heights and widths 有权
标题翻译：制造具有不同高度和宽度的掩埋字线的三维阵列的方法
公开(公告)号：US08987111B2
公开(公告)日：2015-03-24
申请号：US13789930
申请日：2013-03-08
申请人： Jay-Bok Choi , Jiyoung Kim , Hyun-Woo Chung , Sungkwan Choi , Yoosang Hwang
发明人： Jay-Bok Choi , Jiyoung Kim , Hyun-Woo Chung , Sungkwan Choi , Yoosang Hwang
IPC分类号： H01L21/76 , H01L21/762 , H01L21/308 , H01L27/108
CPC分类号： H01L23/5283 , H01L21/3086 , H01L21/76224 , H01L27/10891 , H01L29/0649 , H01L2924/0002 , H01L2924/00
摘要： According to a method of fabricating a semiconductor device, a first mask pattern is used to etch first device isolation layers and active lines or form grooves, in which word lines will be provided. Thereafter, the active lines are etched in a self-alignment manner by using the first mask pattern as an etch mask. As a result, it is possible to suppress mask misalignment from occurring.
摘要翻译：根据制造半导体器件的方法，使用第一掩模图案来蚀刻第一器件隔离层和有源线或形成凹槽，其中将提供字线。此后，通过使用第一掩模图案作为蚀刻掩模，以自对准方式蚀刻有源线。结果，可以抑制掩模未对准的发生。

5. 发明授权

US08809930B2 Semiconductor memory devices 有权
标题翻译：半导体存储器件
公开(公告)号：US08809930B2
公开(公告)日：2014-08-19
申请号：US13742940
申请日：2013-01-16
申请人： Namho Jeon , Jun-Su Kim , Satoru Yamada , Jaehoon Lee , Seunguk Han , Jiyoung Kim , Jin-Seong Lee
发明人： Namho Jeon , Jun-Su Kim , Satoru Yamada , Jaehoon Lee , Seunguk Han , Jiyoung Kim , Jin-Seong Lee
IPC分类号： H01L29/76
CPC分类号： H01L29/7831 , G11C11/403 , G11C11/40615 , G11C11/4097 , G11C2207/2227 , H01L27/105 , H01L27/115
摘要： Semiconductor memory devices may include a write transistor including a first write gate controlling a first source/drain terminal and a second write gate controlling a channel region, and a read transistor including a memory node gate connected to the first source/drain terminal of the write transistor. The first write gate may have a first work function and the second write gate may have a second work function different from the first work function. The first source/drain terminal of the write transistor may not have a PN junction.
摘要翻译：半导体存储器件可以包括写入晶体管，其包括控制第一源极/漏极端子的第一写入栅极和控制沟道区域的第二写入栅极，以及读取晶体管，其包括连接到写入的第一源极/漏极端子的存储器节点栅极晶体管。第一写入门可以具有第一工作功能，并且第二写入门可以具有与第一工作功能不同的第二工作功能。写晶体管的第一源极/漏极端子可以不具有PN结。

6. 发明申请

US20140203357A1 Semiconductor Device and Method of Manufacturing the Same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20140203357A1
公开(公告)日：2014-07-24
申请号：US14162859
申请日：2014-01-24
申请人： Daeik KIM , Jiyoung KIM , Jemin PARK , Nakjin SON , Yoosang HWANG
发明人： Daeik KIM , Jiyoung KIM , Jemin PARK , Nakjin SON , Yoosang HWANG
IPC分类号： H01L29/423 , H01L29/78
CPC分类号： H01L29/4236 , H01L21/26586 , H01L21/823437 , H01L29/7827 , H01L29/7831
摘要： According to a method of manufacturing a semiconductor device, hard mask lines are formed in parallel in a substrate and the substrate between the hard mask lines is etched to form grooves. A portion of the hard mask line and a portion of the substrate between the grooves are etched. A top surface of the etched portion of the substrate between the grooves is higher than a bottom surface of the groove. A conductive layer is formed to fill the grooves. The conductive layer is etched to form conductive patterns in the grooves, respectively.
摘要翻译：根据半导体装置的制造方法，在基板上平行地形成硬掩模线，并且蚀刻硬掩模线之间的基板以形成凹槽。硬掩模线的一部分和凹槽之间的基板的一部分被蚀刻。在槽之间的衬底的蚀刻部分的顶表面高于槽的底表面。形成导电层以填充凹槽。蚀刻导电层以分别在凹槽中形成导电图案。

7. 发明申请

US20130256774A1 SEMICONDUCTOR MEMORY DEVICES 有权
标题翻译：半导体存储器件
公开(公告)号：US20130256774A1
公开(公告)日：2013-10-03
申请号：US13742940
申请日：2013-01-16
申请人： Namho JEON , Jun-Su KIM , Satoru YAMADA , Jaehoon LEE , Seunguk HAN , Jiyoung KIM , Jin-Seong LEE
发明人： Namho JEON , Jun-Su KIM , Satoru YAMADA , Jaehoon LEE , Seunguk HAN , Jiyoung KIM , Jin-Seong LEE
IPC分类号： H01L29/78
CPC分类号： H01L29/7831 , G11C11/403 , G11C11/40615 , G11C11/4097 , G11C2207/2227 , H01L27/105 , H01L27/115
摘要： Semiconductor memory devices may include a write transistor including a first write gate controlling a first source/drain terminal and a second write gate controlling a channel region, and a read transistor including a memory node gate connected to the first source/drain terminal of the write transistor. The first write gate may have a first work function and the second write gate may have a second work function different from the first work function. The first source/drain terminal of the write transistor may not have a PN junction.
摘要翻译：半导体存储器件可以包括写入晶体管，其包括控制第一源极/漏极端子的第一写入栅极和控制沟道区域的第二写入栅极，以及读取晶体管，其包括连接到写入的第一源极/漏极端子的存储器节点栅极晶体管。第一写入门可以具有第一工作功能，并且第二写入门可以具有与第一工作功能不同的第二工作功能。写晶体管的第一源极/漏极端子可以不具有PN结。

8. 发明申请

US20130087842A1 SEMICONDUCTOR DEVICES INCLUDING A VERTICAL CHANNEL TRANSISTOR AND METHODS OF FABRICATING THE SAME 审中-公开
标题翻译：包括垂直通道晶体管的半导体器件及其制造方法
公开(公告)号：US20130087842A1
公开(公告)日：2013-04-11
申请号：US13614457
申请日：2012-09-13
申请人： Jiyoung KIM , Yongchul OH , Kyuhyun LEE , Hyun-Woo CHUNG , Gyoyoung JIN , HyeongSun HONG , Yoosang HWANG
发明人： Jiyoung KIM , Yongchul OH , Kyuhyun LEE , Hyun-Woo CHUNG , Gyoyoung JIN , HyeongSun HONG , Yoosang HWANG
IPC分类号： H01L29/78 , H01L27/108
CPC分类号： H01L27/10885 , H01L27/10855 , H01L27/10876 , H01L27/10888
摘要： According to example embodiments, a semiconductor device includes a lower active portion protruding from a substrate, an active pillar protruding from the lower active portion, a surround gate electrode surrounding the active pillar, a buried bit line extending along a first direction and being on the lower active portion and electrically connected to the lower active portion, and a contact gate electrode contacting both the surround gate electrode and a word line extending a second direction crossing the first direction.
摘要翻译：根据示例性实施例，半导体器件包括从基板突出的下部有源部分，从下部有源部分突出的有源柱，围绕有源支柱的环绕栅电极，沿第一方向延伸的掩埋位线，下部有源部分并且电连接到下部有源部分，以及接触栅极电极，其接触环绕栅极电极和与第一方向交叉的第二方向延伸的字线。

9. 发明授权

US09773546B2 Semiconductor devices including auxiliary bit lines 有权
公开(公告)号：US09773546B2
公开(公告)日：2017-09-26
申请号：US14969843
申请日：2015-12-15
申请人： Joonhee Lee , Jiyoung Kim , Jintaek Park , Seong Soon Cho
发明人： Joonhee Lee , Jiyoung Kim , Jintaek Park , Seong Soon Cho
IPC分类号： G11C13/00 , H01L27/24
CPC分类号： G11C13/0026 , G11C13/0004 , G11C13/0007 , G11C2213/53 , G11C2213/71 , G11C2213/75 , H01L27/24 , H01L27/2454 , H01L27/2481
摘要： Semiconductor devices are provided. A semiconductor device includes a stack of alternating gates and insulating layers. The semiconductor device includes a dummy cell region. The semiconductor device includes a plurality of bit lines and a plurality of auxiliary bit lines. Some of the plurality of auxiliary bit lines have different respective lengths. Related methods of forming semiconductor devices are also provided.

10. 发明申请

US20160343434A1 SEMICONDUCTOR DEVICES INCLUDING AUXILIARY BIT LINES 有权
标题翻译：包括辅助位线的半导体器件
公开(公告)号：US20160343434A1
公开(公告)日：2016-11-24
申请号：US14969843
申请日：2015-12-15
申请人： Joonhee Lee , Jiyoung Kim , Jintaek Park , Seong Soon Cho
发明人： Joonhee Lee , Jiyoung Kim , Jintaek Park , Seong Soon Cho
IPC分类号： G11C13/00
CPC分类号： G11C13/0026 , G11C13/0004 , G11C13/0007 , G11C2213/53 , G11C2213/71 , G11C2213/75 , H01L27/24 , H01L27/2454 , H01L27/2481
摘要： Semiconductor devices are provided. A semiconductor device includes a stack of alternating gates and insulating layers. The semiconductor device includes a dummy cell region. The semiconductor device includes a plurality of bit lines and a plurality of auxiliary bit lines. Some of the plurality of auxiliary bit lines have different respective lengths. Related methods of forming semiconductor devices are also provided.
摘要翻译：提供半导体器件。半导体器件包括交替栅极和绝缘层的堆叠。半导体器件包括虚拟单元区域。半导体器件包括多个位线和多个辅助位线。多个辅助位线中的一些具有不同的相应长度。还提供了形成半导体器件的相关方法。

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