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1. 发明授权

US5107465A Asynchronous/synchronous pipeline dual mode memory access circuit and method 失效
标题翻译：异步/同步管道双模存储器访问电路和方法
公开(公告)号：US5107465A
公开(公告)日：1992-04-21
申请号：US407403
申请日：1989-09-13
申请人： Jimmy Fung , Jiu An , David L. Campbell , Steven Shyu
发明人： Jimmy Fung , Jiu An , David L. Campbell , Steven Shyu
IPC分类号： G11C11/413 , G06F5/10 , G11C11/407 , G11C11/408 , G11C11/418 , H03K3/037
CPC分类号： G06F5/10 , H03K3/0372
摘要： A pipeline memory access circuit has a memory address buffer for buffering memory addresses. The buffer has a first and a second pass gate, and each of the pass gates has a pair of complementary metal-oxide-semiconductor (CMOS) transistors. An apparatus is provided for selectively switching the buffer between an asynchronous and a synchronous mode of operation. The switching apparatus includes circuits for alternately opening and closing the first and second pass gates when the buffer is in its synchronous mode of operation and for simultaneously opening both of the pass gates when the buffer is in its asynchronous mode of operation.

2. 发明授权

US6061361A Time multiplexed scheme for deadlock resolution in distributed arbitration 失效
标题翻译：分布式仲裁中的死锁解决时间复用方案
公开(公告)号：US6061361A
公开(公告)日：2000-05-09
申请号：US879202
申请日：1997-06-19
申请人： Jiu An , Shashank Merchant
发明人： Jiu An , Shashank Merchant
IPC分类号： G06F15/16 , G06F9/52 , G06F13/36 , G06F13/362 , G06F13/364 , G06F13/368 , G06F15/177 , H04L12/43 , B41B15/00 , G06F15/00 , H04J3/02 , H04L12/40
CPC分类号： G06F13/364
摘要： An arbitration system resolves bus contention problems by assigning an exclusive portion of a clock signal to a corresponding arbiter. The system includes shared resources and one or more requesting agents that require access to more than one of the shared resources. The system uses two arbiters, each which communicate the status of a respective shared bus to the other arbiter. A first agent requesting access to a first bus is only granted access during a first portion of a clock signal and based on the availability of a second bus. A second agent requesting access to a second bus is only granted access during a second portion of the clock signal and based on an availability of the first bus.
摘要翻译：仲裁系统通过将时钟信号的独占部分分配给对应的仲裁器来解决总线争用问题。系统包括共享资源和一个或多个需要访问多个共享资源的请求代理。该系统使用两个仲裁器，每个仲裁器将相应的共享总线的状态传达给另一个仲裁器。请求访问第一总线的第一代理只允许在时钟信号的第一部分期间访问，并且基于第二总线的可用性。请求访问第二总线的第二代理仅在时钟信号的第二部分期间并且基于第一总线的可用性被授权访问。

3. 发明授权

US5920227A Zero current draw circuit for use during a bonding option 失效
标题翻译：焊接期间使用的零电流拉制电路
公开(公告)号：US5920227A
公开(公告)日：1999-07-06
申请号：US876213
申请日：1997-06-16
申请人： Jiu An
发明人： Jiu An
IPC分类号： H01L27/04 , H01L21/60 , H01L21/82 , H01L21/822 , H03K19/173 , G05F3/02
CPC分类号： H01L24/06 , H01L24/49 , H03K19/1731 , H01L2224/05553 , H01L2224/05554 , H01L2224/48227 , H01L2224/49113 , H01L2924/00014 , H01L2924/01004 , H01L2924/01007 , H01L2924/01014 , H01L2924/01033 , H01L2924/01082 , H01L2924/10253 , H01L2924/1306 , H01L2924/14 , H01L2924/19043
摘要： A circuit that is coupled to a bonding pad of an integrated circuit structure for reducing the leakage current through the structure to approximately zero when a bonding option is selected. The current path through the integrated circuit structure is removed by turning off a circuit element upon application of a control signal from the integrated circuit structure.
摘要翻译：耦合到集成电路结构的焊盘的电路，用于当选择接合选项时，将通过结构的漏电流减小到大约为零。通过在从集成电路结构施加控制信号时，通过关断电路元件来去除通过集成电路结构的电流路径。

4. 发明授权

US5860025A Precharging an output peripheral for a direct memory access operation 失效
标题翻译：为直接存储器访问操作预充电输出外设
公开(公告)号：US5860025A
公开(公告)日：1999-01-12
申请号：US677406
申请日：1996-07-09
申请人： David G. Roberts , Robert Alan Williams , Glen William Gibson , Jiu An , RamKrishna Vepa , Henry Yeh , Din-I Tsai
发明人： David G. Roberts , Robert Alan Williams , Glen William Gibson , Jiu An , RamKrishna Vepa , Henry Yeh , Din-I Tsai
IPC分类号： G06F12/10 , G06F13/28 , G06F13/12 , G06F13/14
CPC分类号： G06F12/1081 , G06F13/28
摘要： A data transfer method with peripheral precharge wherein a starting portion of an output data block targeted for a peripheral is transferred to an output buffer for the peripheral using programmed I/O or slave cycles and wherein a virtual address of the output data block is translated into a physical address while the peripheral begins transferring the starting portion from the output buffer and over an output path. A direct memory access operation by the peripheral transfers a remainder portion of the output data block into the output buffer.
摘要翻译：一种具有外围预充电的数据传输方法，其中针对外设的输出数据块的起始部分使用编程的I / O或从属周期传送到外围设备的输出缓冲器，并且其中输出数据块的虚拟地址被转换为物理地址，而外设开始从输出缓冲器和输出路径传送起始部分。由外设的直接存储器存取操作将输出数据块的剩余部分传送到输出缓冲器。

5. 发明授权

US06785849B1 Arrangement for reducing a media independent interface speed in a network switch emulation system 失效
标题翻译：用于降低网络交换机仿真系统中媒体独立接口速度的布置
公开(公告)号：US06785849B1
公开(公告)日：2004-08-31
申请号：US09779483
申请日：2001-02-09
申请人： Harand Gaspar , Shashank Merchant , Jiu An
发明人： Harand Gaspar , Shashank Merchant , Jiu An
IPC分类号： G06F1100
CPC分类号： H04L43/50
摘要： A test system includes a switch emulator, a network test device, and an interface converter. The switch emulator is configured for transmitting first network data on a first media independent interface based on a first interface clock, and the network test device configured for transmitting second network data on a second media independent interface based on a second interface clock. The interface converter, having inverted media independent interfaces, is configured for transferring the first and second network data between the first and second media independent interfaces, and supplying the first and second interface clocks based on an external clock generated by the switch emulator. Hence, network data can be passed between the switch emulator and the network test device according to network protocols, even if the switch emulator is operating at relatively slow speeds.
摘要翻译：测试系统包括开关仿真器，网络测试设备和接口转换器。交换机仿真器被配置为基于第一接口时钟在第一媒体独立接口上发送第一网络数据，并且所述网络测试设备被配置为基于第二接口时钟在第二媒体独立接口上发送第二网络数据。具有反向媒体独立接口的接口转换器被配置为在第一和第二媒体无关接口之间传送第一和第二网络数据，并且基于由开关仿真器产生的外部时钟提供第一和第二接口时钟。因此，即使交换机仿真器以相对较慢的速度运行，网络数据也可以根据网络协议在交换机仿真器和网络测试设备之间传递。

6. 发明授权

US06721310B2 Multiport non-blocking high capacity ATM and packet switch 有权
标题翻译：多端口非阻塞高容量ATM和分组交换机
公开(公告)号：US06721310B2
公开(公告)日：2004-04-13
申请号：US10000272
申请日：2001-11-02
申请人： Zheng Liu , Jiu An , Terry Xian , Ronald P. Novick
发明人： Zheng Liu , Jiu An , Terry Xian , Ronald P. Novick
IPC分类号： H04L1228
CPC分类号： G01N33/586
摘要： A multiport non-blocking high capacity ATM and packet switch is a single chip switching solution for ATM and packet systems. It is capable of 8×8 switching of 800 Mbit/s per port in both directions. The ports support UTOPIA Level 2 interfaces. The switch is non-blocking and lossless, incorporating a backpressure mechanism for eliminating congestion toward any one port. The switch supports prioritized and variable size cell and packet switching.
摘要翻译：多端口非阻塞高容量ATM和分组交换机是用于ATM和分组系统的单芯片交换解决方案。它能够在双向方向上每端口800兆比特的8×8切换。端口支持UTOPIA 2级接口。该开关是非阻塞和无损的，结合了一个背压机制，用于消除任何一个端口的拥塞。交换机支持优先级和可变大小小区和分组交换。

7. 发明授权

US5184129A Switchable DAC with current surge protection 失效
标题翻译：具有电流浪涌保护功能的可切换DAC
公开(公告)号：US5184129A
公开(公告)日：1993-02-02
申请号：US712146
申请日：1991-06-06
申请人： Jimmy Fung , Jiu An , David L. Campbell , Steven Shyu
发明人： Jimmy Fung , Jiu An , David L. Campbell , Steven Shyu
IPC分类号： H03M1/00 , H03M1/66 , H03M1/74
CPC分类号： H03M1/66 , H03M1/002 , H03M1/742
摘要： In a CMOS DAC having a plurality of stages a control circuit for selectively switching said DAC between a sleep mode and a normal operating mode with little, if any, surge current resulting therefrom. In the control circuit there is provided control transistors responsive to control signals for applying a reverse biasing potential to a reference voltage transistor and a digital input transistor in each of the stages at a rate such that the rate of change of current in the reference voltage transistor is less than a predetermined magnitude, e.g. less than 5 ma/nsec. when said DAC is switched to its sleep mode and transistor means responsive to control signals for first applying a predetermined forward biasing potential to a bias transistor and thereafter changing said reverse potential applied to said reference voltage transistor to a predetermined reference voltage and removing said reverse bias potential from said digital input transistor when said DAC is switched to its normal operating mode.
摘要翻译：在具有多级的CMOS DAC中，用于在睡眠模式和正常操作模式之间选择性地切换所述DAC的控制电路，由此产生的浪涌电流很少（如果有的话）。在控制电路中，提供控制晶体管，其响应于控制信号，以将反向偏置电位施加到每个级中的参考电压晶体管和数字输入晶体管，其速率使得参考电压晶体管中的电流变化率小于预定的大小，例如小于5马力/纳秒。当所述DAC切换到其睡眠模式时，晶体管装置响应于控制信号，首先将预定的正向偏置电位施加到偏置晶体管，然后将施加到所述参考电压晶体管的所述反向电位改变为预定参考电压，并且去除所述反向偏置当所述DAC切换到其正常操作模式时，所述数字输入晶体管的电位。

8. 发明授权

US5023614A Switchable DAC with current surge protection 失效
标题翻译：具有电流浪涌保护功能的可切换DAC
公开(公告)号：US5023614A
公开(公告)日：1991-06-11
申请号：US407447
申请日：1989-09-13
申请人： Jimmy Fung , Jiu An , David L. Campbell , Steven Shyu
发明人： Jimmy Fung , Jiu An , David L. Campbell , Steven Shyu
IPC分类号： H03M1/66 , H03M1/00 , H03M1/74
CPC分类号： H03M1/002 , H03M1/742
摘要： In a CMOS DAC having a plurality of stages a control circuit for selectively switching said DAC between a sleep mode and a normal operating mode with little, if any, surge current resulting therefrom. In the control circuit there is provided control transistors responsive to control signals for applying a reverse biasing potential to a reference voltage transistor and a digital input transistor in each of the stages at a rate such that the rate of change of current in the reference voltage transistor is less than a predetermined magnitude, e.g. less than 5 ma/nsec. when said DAC is switched to its sleep mode and transistor means responsive to control signals for first applying a predetermined forward biasing potential to a bias transistor and thereafter changing said reverse bias potential applied to said reference voltage transistor to a predetermined reference voltage and removing said reverse bias potential from said digital input transistor when said DAC is switched to its normal operating mode.

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